Data cache array having multiple content addressable fields per

Details Data cache array having multiple content addressable fields per Data cache array having multiple content addressable fields per

1994-10-05

1998-09-08

Swann, Tod R.

395453, 395455, 395454, G06F 1208

Patent

active

058058559

ABSTRACT:
An interleaved data cache array which is divided into two subarrays. Each subarray includes a plurality of cache lines wherein each cache line includes a selected block of data, a parity field, a content addressable field containing a portion of an effective address for the selected block of data, a second content addressable field contains a portion of the real address for the selected block of data and a data status field. By utilizing two separate content addressable fields for the effective address and real address offset and alias problems may be efficiently resolved. The data cache is preferably arranged as an eight way set-associative cache wherein each congruence class includes up to eight entries having identical low order address bits. A separate effective address port and real address port permit parallel access to the cache without conflict in separate subarrays and a subarray arbitration logic circuit is provided for attempted simultaneous access of a single subarray by both the effective address port and the real address port.

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