Data cache and method for handling memory errors during copy-bac

Details Data cache and method for handling memory errors during copy-bac Data cache and method for handling memory errors during copy-bac

1991-02-05

1994-03-15

Atkinson, Charles E.

Boots, shoes, and leggings

36424341, 364243, G06F 100

Patent

active

052952592

ABSTRACT:
Apparatus and method of a data cache which provides for the handling of errors during data copy-back from a data cache write buffer to external memory in a processing system including a processor. When data requested by the processor at an addressed storage location of the data cache is data which is valid, modified, and other than the data requested by the processor, the data is first transferred to the data cache write buffer and then written back to external memory after the requested data is fetched from a memory bus. If an error occurs during the write back of the data from the write buffer to external memory, the data is transferred from the write buffer to the storage location of the data cache originally addressed by the processor before the memory bus is released.

REFERENCES:
patent: 4392200 (1983-07-01), Arulpragasam et al.
patent: 4933835 (1990-06-01), Sachs et al.
patent: 4995041 (1991-02-01), Hetherington et al.
patent: 5025366 (1991-06-01), Baror
patent: 5155824 (1992-10-01), Edenfield et al.
patent: 5197144 (1993-03-01), Edenfield et al.

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