Data bus selector/control circuit for dynamic ram

Details Data bus selector/control circuit for dynamic ram Data bus selector/control circuit for dynamic ram

1992-08-19

1994-12-20

LaRoche, Eugene R.

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

365201, 365203, G11C 800, G11C 700

Patent

active

053750969

ABSTRACT:
A data bus selector/control amplifier comprises a plurality of basic circuit blocks for controlling the connection of the bus lines of a first data bus comprising a plurality of bus lines and a second data bus comprising a plurality of bus lines. The basic circuit blocks provided correspond to each of the bus lines of the second data bus. Each of the basic circuit blocks sends written data or precharging current to the second data bus via its own data amplifier. Second and third transfer gates retain the data to be written into and data to be read out from the data amplifier.

REFERENCES:
patent: 4926387 (1990-05-01), Madland
patent: 4931995 (1990-06-01), Okasawa et al.
patent: 4991139 (1991-02-01), Takahashi et al.
patent: 5088063 (1992-02-01), Matsuda et al.
patent: 5191555 (1993-03-01), Tabacco et al.
patent: 5208778 (1993-05-01), Kumanoya et al.

Affiliated with

Also associated with

Rating

Data bus selector/control circuit for dynamic ram does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Data bus selector/control circuit for dynamic ram, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Data bus selector/control circuit for dynamic ram will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2389523