Data bus protocol for high speed chip to chip data transfer

Details Data bus protocol for high speed chip to chip data transfer Data bus protocol for high speed chip to chip data transfer

1995-02-14

1996-08-27

Pan, Daniel

Boots, shoes, and leggings

3642408, 3642295, 3642292, 3642305, 3642317, 3642401, 3642568, 364DIG1, 364DIG2, 39518501, G06F 946, G06F 13362, G06F 1342, G06F 1340

Patent

active

055510523

ABSTRACT:
A protocol for communication through a bus controller to control data transfers between a host processing platform and the data bus of a bit map printer. This protocol is optimized for a data bus which connects a number of ASIC accelerator cards in addition to the printer, disk controller, bus controller and other typical system cards. The basic data transfer cycle transfers eight data words on the bus between ASIC's, I/O devices, printer and any other devices.

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patent: 5179530 (1993-01-01), Genusov et al.
patent: 5243238 (1993-09-01), Kean
patent: 5367643 (1994-11-01), Chang et al.

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