Data bus protocol for computer graphics system

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Details

395310, 395850, G06F 1338

Patent

active

056713738

ABSTRACT:
An apparatus and method for transferring data between first and second circuit blocks of a computer graphics system are provided. The first and second circuit blocks are interconnected by a data bus having n bits. The apparatus includes a circuit in the first circuit block for sequentially transmitting data words from the first circuit block to a second circuit block on the data bus. The data words include one or more long data words having more than n bits. The apparatus further includes a register in the first circuit block for storing bits of the long data words in excess of n bits, and a controller in the first circuit block for loading the bits of the long data words in excess of n bits into the register and for combining the bits of the long data words stored in the register into a composite data word for transmission to the second circuit block. The composite data word may include a short data word having less than n bits. In a preferred embodiment, Z coordinate data words having 40 bits are transmitted with an 8 bit command word over a 32 bit data bus without extra bus cycles.

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patent: 4525804 (1985-07-01), Mosier et al.
patent: 4716527 (1987-12-01), Graciotti
patent: 5113369 (1992-05-01), Kinoshita
patent: 5280598 (1994-01-01), Osaki et al.
patent: 5394528 (1995-02-01), Kobayashi et al.
patent: 5423009 (1995-06-01), Zhu

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