Data bus including address request line for allowing request for

Details Data bus including address request line for allowing request for Data bus including address request line for allowing request for

1996-02-09

1997-10-21

Harvey, Jack B.

395290, 395855, G06F 1328

Patent

active

056806434

DESCRIPTION:

BRIEF SUMMARY
FIELD OF THE INVENTION

This invention relates to apparatus and method for data processing having a data bus. More particularly, this invention relates to such apparatus and method having a bus master circuit and a bus slave circuit.


BACKGROUND OF THE INVENTION

It is known to provide master and slave bus architectures in which a bus master is responsible for initiating and controlling data transfer on the data bus, with the one or more bus slaves serving to respond to transactions initiated by the bus master. Such architectures are readily expandable and allow diverse bus slaves to be managed by a single bus master. A disadvantage of such architectures is that the bus master must be able to accommodate differing performance parameters in the diverse bus slaves with which it communicates, e.g. the rate at which data can be transferred to or from a particular bus slave or the addressing requirements of each bus slave.
This is particularly the case in the context of high performance transfer modes via the data bus where not all of the bus slaves are likely to be able to deal with such high performance operation. This creates a problem in that, as a new bus slave is added to a system, the bus master may need to be reprogrammed/ reconfigured to take account of the performance characteristics of that new bus slave. This is a disadvantageous additional complexity in developing a new system where ideally one merely wishes to attach the various component parts to the data bus without having to alter the component parts for that particular combination.
European Patent Application EP-A-O 348 113 discloses a programmable memory controller that supports burst mode transfers and signals to a processor when a burst mode must terminate.
IBM Technical Disclosure Bulletin, vol. 33, no. 6B, November 1990, New York, U.S., page 422, "Computer system channel performance enhancement via address boundary release" discloses a memory controller that inserts wait states as required at page boundaries.
Wescon Conference Record, vol, 34, November 1990, North Hollywood, U.S., pages 29-32, Amitoi et al, "Burst mode memories improve cache design" discloses an integrated circuit including a bus master and a bus slave.


SUMMARY OF THE INVENTION

Viewed from one aspect, the invention provides apparatus and method for data processing including: a data bus for carrying data words and address words; and a bus master circuit for initiating a burst mode transfer via the data bus in which the bus master generates an address word, and the address word specifies a start address of a sequence of addresses, relating to respective ones of a plurality of data words to be transferred via the data bus in successive processing cycles; and a bus slave circuit for receiving the plurality of data words of the burst mode transfer from the bus master circuit via the data bus; wherein the data bus includes an address request signal line; and the bus slave circuit includes means for generating an address request signal when an address word is required by the bus slave circuit in a next processing cycle; and the bus master circuit includes means responsive to an address request signal received from the bus slave circuit via the address request signal line for interrupting the burst mode transfer and generating a further address word in said next processing cycle.
A burst mode transfer from a bus master circuit to a bus slave circuit is a particularly efficient and high performance mode of operation. Where the data being transferred will be associated with a predetermined sequence of addresses within the bus slave circuit, starting from an initial specified address, only the initial address need be specified. Thus, a single address word might be followed by hundreds or thousands of data words. The increase in the number of data words transferred per address word needing to be specified has the advantage of decreasing the time required to transfer a given block of data words.
Unfortunately, not all bus slaves are able to fully deal with such burst mode transfer

REFERENCES:
patent: 4851990 (1989-07-01), Johnson et al.
patent: 5553310 (1996-09-01), Taylor et al.
Zwie Amatai, David C. Wyland, "Burst Mode Memories Improve Cache Design", IRE Wescon Conference Record, North Hollywood, vol. 34 Nov. 1990.
Zwie Amitai, David C. Wyland, "Burst Mode Memories Improve Cache Design", IRE Wescon Conference Record, North Hollywood, California, vol. 34, Nov. 1990, pp. 29-32.

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