Data bus enable verification logic

Details Data bus enable verification logic Data bus enable verification logic

1988-09-13

1990-08-28

Atkinson, Charles E.

Excavating

371 165, 371 571, G06F 1100

Patent

active

049531670

ABSTRACT:
Logic checking circuits are provided for verifying whether or not the data bus enable logic circuits are operating properly in response to operational commands to transmit or to NOT transmit data. The transmit latches in the bus interface logic circuits are continuously monitored to determine if they are set or NOT set in a position to enable transmission of data or NOT to enable transmission of data to a bus. Transmit gating circuit means are couple to the output of said transmit latches for determining if all of the transmit latches are in the same state and are in the state ordered by the central controller, and for determining whether the state ordered by the central controller occurs in the exact time period during which the command to transmit should be executed.

REFERENCES:
patent: 3164727 (1965-01-01), Heyda
patent: 3539786 (1970-11-01), Raehpour
patent: 3614735 (1971-10-01), Mauger et al.
patent: 3812337 (1974-05-01), Crosley
patent: 4020293 (1977-04-01), Ashley

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