Data bus architecture compatible with 32-bit and 64-bit processo

Details Data bus architecture compatible with 32-bit and 64-bit processo Data bus architecture compatible with 32-bit and 64-bit processo

1996-01-11

1997-04-01

Harvey, Jack B.

395280, 395281, G06F 1300

Patent

active

056175469

ABSTRACT:
A removable CPU module for use in a data processing system. The CPU module includes at least one CPU having a first data width, and a first data bus of the same data width coupled to the CPU. A connector is coupled to the first data bus for connecting to a circuit board having a second data bus. The second data bus has a second data width which is different from the first data width. The CPU module is configured such that it is compatible with the second data bus. In one embodiment, the removable CPU module includes a third data bus coupled to the first data bus and the connector, which is a duplicate of and connected in parallel with the first data bus. The third data bus facilitates compatibility between the CPU module and the second data bus.

REFERENCES:
patent: 4443846 (1984-04-01), Adcock
patent: 5301281 (1994-04-01), Kennedy
patent: 5321827 (1994-06-01), Lu et al.

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