Data buffering system for plural data memory arrays

Details Data buffering system for plural data memory arrays Data buffering system for plural data memory arrays

1996-11-20

1999-03-02

Dinh, Dung C.

G06F 1502

Patent

active

058782800

ABSTRACT:
A video server includes a plurality of input/output devices coupled to a plurality of memory arrays via a commutator. Within each memory array, a buffer is operative to collect data for transfer to and/or from an array controller. Each memory array includes an error correction system providing parity-based RAID type error correction. A plurality of disk controllers each having a FIFO buffer and respective pluralities of disk memories are commonly coupled to a communication bus which in turn is coupled to the error correction system by a FIFO buffer. A segment buffer having a plurality of low cost memory devices which are configured to provide a plurality of ring buffers is coupled to the data bus. An access logic circuit controls the data flow through the FIFO buffer and a central processing unit is operative to provide address sequence upon the communication bus for controlling data transfer to and from the segment buffer. An arbitrator is operative to resolve contentions between the FIFO buffer, the central processing unit, and the disk controllers for access to the segment buffer. The arbitrator utilizes an overall contention resolution priority which includes a rotating subpriority for resolving contentions among the plural disk controllers.

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