Data buffer

Details Data buffer Data buffer

1976-05-20

1977-10-18

Robinson, Thomas A.

Telegraphy

Systems

Line-clearing and circuit maintenance

H04L 700

Patent

active

040547477

ABSTRACT:
A data buffer makes use of a plurality of buffer storage cells into which serial bit streams are sequentially written, in order to obtain correction for phase jitter. A write clock signal is derived from the serial bit stream and is used to sequentially write the digits into the cells. A stable clock source is used to provide the basic timing for sequentially reading the bits out from the buffer storage cells, and a logic circuit is used in conjunction therewith to obtain the retimed serial bit stream. The write and read timing signals should have a maximum time separation to allow for maximum correction of phase jitter, and it is critical that the write and read signals should alternate. A monitor and reset circuit compares a selected write signal with a selected read signal and, where a violation of the alternating write-read condition occurs, the circuit resets the write timing and holds it until the read timing has attained a particular state.

REFERENCES:
patent: 3531777 (1970-09-01), West
patent: 3803356 (1974-04-01), Hausmann
patent: 3867579 (1975-02-01), Colton et al.

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