Static information storage and retrieval – Read only systems – Magnetic
Reexamination Certificate
2002-01-25
2003-04-15
Tran, M. (Department: 2818)
Static information storage and retrieval
Read only systems
Magnetic
C365S225500
Reexamination Certificate
active
06549446
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to solid state data storage devices, and particularly although not exclusively, to solid state storage devices having one or more two-dimensional arrays of memory elements.
BACKGROUND TO THE INVENTION
The invention relates to solid state memory devices such as existing semi conductor technologies, for example dynamic random access memory (DRAM), FLASH and static random access memory (SRAM) or other technologies, for example magnetic random access memory (MRAM). In these devices, memory cells are arranged in one or more two-dimensional arrays addressed by word lines (rows) and bit lines (columns). To read and write cells in the arrays, one row and one or more bit lines are ‘selected’ to access the required cells. Depending upon the implementation, there may be one read/write circuit per column (enabling all bits on the row to be read/written simultaneously) or read/write circuits may be multiplexed or shared between columns.
In DRAM, the memory cell uses a capacitor. A charge held on this capacitor determines the state of the cell (1 or 0). In FLASH memories, the state of a cell is determined by a charge trapped in a floating node within the memory cell. In MRAM, the state of a cell is determined by the electrical resistance resulting from the orientation of a magnetic field within the cell.
SUMMARY OF THE INVENTION
In arrays of memory cells as described above, the operation and performance of individual cells can be influenced by the data held in other cells along selected word and bit lines. The data in the cells on a particular word or bit line can change the electrical characteristics (such as resistance, capacitance) of that word or bit line and therefore compromise the performance of the read and write circuits. Extremes of this effect may be encountered when the memory cells are all at a ‘1’ state or all at a ‘0’ state along a word or bit line. This typically occurs, for example, following reset conditions when an entire memory array may be initialized to a fixed value. This effect is particularly pronounced in MRAM arrays such as those described in the applicants patent application EP 0918334 titled ‘Solid state memory with magnetic storage cells’, as DC currents flow through the array of memory cells when reading and writing. Specific problems include:
A high number of ones or zeros introduces a DC bias into a word or bit line. The read and write circuits have to cope with this bias, adding complexity to the read and write circuits.
Write and read signals will be skewed by the bias, that is to say by the different electrical loads presented by the word or bit line as the density of ones and zeros changes along the word or bit line. This will affect the read/write error rate performance of these circuits.
Parasitic or leakage paths through unselected cells on the word and bit line(s) which are being accessed will also change. Minimizing these leakage paths is critical to operation of MRAM arrays such as those described in European patent application EP 0918334 entitled ‘Solid state memory with magnetic storage cells’.
Pattern dependent faults may occur due to concentration of ones and zeros in areas of the array.
Similar problems are experienced in conventional DRAM and SRAM devices, but to a lesser degree than in MRAM devices.
The invention provides a method for storing data in an array such that the above problems are minimized. Specific implementations of the invention aim to balance the number of 0's and 1's in any word or bit line in an array. When applied to an array of memory elements, the term balanced means that within an individual word or bit line in the array, an equal number of 1's occur as do 0's. The term substantially balanced is construed accordingly, as a case where a substantially similar number of 1's occur as do 0's.
Data in the array is coded so as to substantially balance the number of 1's and 0's on each word or bit line. This coding also avoids long contiguous runs of 1's and 0's on each word or bit line.
By storing data in a two-dimensional array in a balanced manner, the problem of large variations in word and bit line characteristics is avoided. DC bias on word and bit lines is minimized and thus the data affecting electrical characteristics of word and bit lines are minimized. This has benefits in improved performance and reliability of the array, and a lower error rate when reading the array. The design and complexity of the read/write circuits is also reduced, since such a wide variation of DC conditions does not need to be accommodated and peak write currents in the array are reduced.
Additionally, an effect of the data affecting electrical characteristics of a plurality of word lines and bit lines is minimized for each word line and bit line.
Specific implementations and methods according to the present invention may overcome a problem of word and bit line characteristic variations, without the need for adding additional complexity to read-write drive circuitry to overcome the electrical characteristic variations.
Specific implementations according to the present invention may avoid degradation of read-write performance due to electrical loading of bit lines and word lines by extended data sequences of all ‘1’s or all ‘0’s stored in individual memory elements along a word line or bit line.
According to a first aspect of the present invention there is provided a method of writing incoming data to a data storage device comprising an array of memory elements arranged in rows and columns and accessible by a plurality of data access lines said method comprising the steps of:
receiving said incoming data as a plurality of ones and zeros;
coding said incoming data to produce a coded data, said coded data comprising a plurality of ones and zeros and said coding comprising applying an output of a pseudo random bit sequence generator to said incoming data;
storing said coded data in said array of memory elements, such that a plurality of said ones and zeros comprising said coded data are stored along each row, and a plurality of ones and zeros comprising said coded data are stored along each column, such that:
a substantially similar number of ones and zeros occur along each said row of memory elements; and
a substantially similar number of ones and zeros occur along each said column of memory elements.
By the term “substantially similar” it is meant that a number of ones and zeros stored along each row or column are equalized in said coded data, as compared with the equivalent situation of storing said incoming data along the same rows or columns. A disparity between the number of ones and the number of zeros in any block of said coded stored data may be less than in an equivalent block of said incoming data. Ideally, an equal number of ones as zeros will occur along each said row of memory elements, and an equal number of ones and zeros will occur along each said column of memory elements.
Preferably, for each said row a distribution of said ones and zeros of said row is such that significant spatial concentrations of ones and significant spatial concentrations of zeros are avoided.
Preferably, for each said column, a distribution of said ones and zeros of said column is such that significant spatial concentrations of ones and significant spatial concentrations of zeros are avoided along said column.
Preferably said incoming data is combined with a predetermined code value, such that said combination of said incoming data and said coding produces said coded data having a relatively more even distribution of ones and zeros in said coded data than in said incoming data.
Preferably said step of coding said incoming data comprises coding said incoming data to produce a pseudo-randomized coded data. An output of a pseudo random bit sequence generator may be applied to said incoming data.
According to a second aspect of the present invention there is provided a method of reading coded data from a data storage device comprising an array of memory ele
Bramhall Peter Joseph
Lloyd-Jones Kevin
McCarthy Dominic P.
Morley Stephen
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