Data-array processing system wherein parallel processors access

Details Data-array processing system wherein parallel processors access Data-array processing system wherein parallel processors access

1993-02-01

1996-07-23

Swann, Tod R.

Boots, shoes, and leggings

395495, 395427, 395474, 395800, 36424291, 3642462, 36493141, 36493146, 364DIG1, G06F 1300, G06F 1206

Patent

active

055398987

ABSTRACT:
A data array processing system comprises a memory system for storing an array of data elements and addressable by a single address, a plural number N of processors (PROC(0)-(15)) capable of processing data elements in parallel, and an address bus. In order to allow parallel access to the memory system where possible, but permit the processors also to access different addresses, each processor is selectable to supply its respective required address (xq, yq) via the address bus to the memory system to access the memory, and each non-selected processor is operable to determine whether it requires access to the address (xq, yq) on the bus, and if so to access the memory system at the same time as the selected processor.

REFERENCES:
patent: 4622632 (1986-11-01), Tanimoto et al.
patent: 4908751 (1990-03-01), Smith
patent: 5247649 (1993-09-01), Bandoh

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