Data and forward error control coding techniques for digital sig

Details Data and forward error control coding techniques for digital sig Data and forward error control coding techniques for digital sig

1991-09-10

1992-09-01

Logan, Sharon D.

Coded data generation or conversion

Digital code to digital code converters

To or from minimum d.c. level codes

341 59, 341 94, H03M 730, H03M 1300, H03M 746

Patent

active

051443040

ABSTRACT:
Input values are data encoded for improved signal characteristics (e.g., limited maximum run length and limited cumulative DC-offset) so as to form "data codewords, " and then a number of the data codewords, collectively referred to as a block, are error protection encoded, preferably using a conventional linear and sytematic forward error control ("FEC") code, to yield an FEC code block. Preferably, an FEC code block is formed by generating a number of check bits or FEC bits equal to the number of data codewords in the block, and then concatenating one FEC bit and its binary complement with each data codeword, so that one FEC bit and its complement is interposed between each successive codeword.

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patent: 4003041 (1977-01-01), Van Duuren et al.
patent: 4387364 (1983-06-01), Shirota
patent: 4389636 (1983-06-01), Riddle, Jr.
patent: 4394641 (1983-07-01), Ratigalas
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patent: 4833470 (1989-05-01), Iketani
Shu Lin, Daniel J. Costello, Jr., "Error Control Coding" pp. 498-503, 1983.
A. X. Widmer, P. A. Franaszek, "A DC-Balanced, Partioned Block, 8B/10B Transmission Code", IBM J. Res. Develop., vol. 27, No. 5, Sep. 1983 pp. 440-451.

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