Data and clock recovery system for data communication controller

Details Data and clock recovery system for data communication controller Data and clock recovery system for data communication controller

1982-08-30

1985-04-23

Safourek, Benedict V.

Pulse or digital communications

Spread spectrum

Direct sequence

375 87, 370108, H04L 706

Patent

active

045134278

ABSTRACT:
A data and clock recovery system is provided in the signal handling receiver (SHRx) stage of an integrated MOS circuit data communication controller to provide accurate sampling of an incoming data packet for recovery of the data and data clock, regardless of differences in the electrical and environmentally affected characteristics of the circuit elements comprising the integrated MOS/VLSI semiconductor chip. The system comprises a delay means including a plurality of delay stages to generate a transition pulse for every transition in the data packet, a similar delay means to apply a predetermined amount of unit delay to all of the transition pulses, both data transition pulses and between bit transition pulses, means to develop a mask from the delayed transition pulses representative of the time occurrence of any between bit transitions, means to apply the mask to the incoming data packet whereby the extraneous between bit transition pulses are removed therefrom, and means coupled to the delay means to calibrate the delay means by ensuring that each of its delay stages continuously impose a predetermined unit delay per stage.

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Mead & Conway, Introduction to VLSI Systems, Addison-Wesley Pub. Co., pp. 17-18, 67, 229-236 (1980).

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