Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system
Reexamination Certificate
2008-09-02
2008-09-02
DeCady, Albert (Department: 2121)
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
C716S030000, C716S030000, C703S014000
Reexamination Certificate
active
10010238
ABSTRACT:
A method for data analysis of power modeling for a microprocessor has been developed. The method takes multiple values of power data from a power modeling simulator and generates summary data to characterize the power data behavior. Summary data views include results characterizing behavior in a single cycle and behavior across multiple cycles. Data is viewed both at an absolute level to characterize total power and relative to previous levels to characterize power derivatives. Summary data is derived from power generated every cycle when running specific benchmark programs on the power simulator.
REFERENCES:
patent: 5136528 (1992-08-01), Fordham et al.
patent: 5349542 (1994-09-01), Brasen et al.
patent: 5555201 (1996-09-01), Dangelo et al.
patent: 5559997 (1996-09-01), Tsuchida et al.
patent: 5677856 (1997-10-01), Tani
patent: 5812433 (1998-09-01), Kawabata et al.
patent: 5815693 (1998-09-01), McDermott et al.
patent: 5844822 (1998-12-01), Yoshida
patent: 5926394 (1999-07-01), Nguyen et al.
patent: 6009256 (1999-12-01), Tseng et al.
patent: 6014510 (2000-01-01), Burks et al.
patent: 6125334 (2000-09-01), Hurd
patent: 6397172 (2002-05-01), Gurney
patent: 6496957 (2002-12-01), Kumagai
Christesen et al., “Analog and Mixed-Signal Modeling Using the VHDL-AMS Language” 36th Design Automation Conference 1999. p. 1-199.
Tiwari et al., “Power Analysis of Embedded Software: A First Step Towards Software Power Minization” IEEE 1994. p. 437-445.
Greenhill-D. “The Impact of Technology Scaling on Microprocessor Design” Seminar abstract 1999 p. 1.
Booba et al., “IC Power Distribution Challenges” Jan. 2001. International Conference on Computer-Aided Design IEEE/ACM p. 643-650.
Bogliolo et al., “Gate-Level Power and Current Simulation of CMOS Integrated Circuits” 1997 IEEE p. 473-488.
Brown et al., “Overview of Complementary GaAs Technology for High-Speed VLSI Circuits” 1998 IEEE p. 47-51.
Bogliolo et al., “Node Sampling: a Robust RTL Power Modeling Approach” 1998 ACM p. 461-467.
Gupta et al., “Analytical Models for RTL Power Estimation of Combinational and Sequential Circuits” 2000 IEEE p. 808-813.
Hsiao et al., “Effects of Delay Models on Peak Power Estimation of VLSI Sequential Circuits”, IEEE 1997 p. 45-51.
Mudge, T., “Power: A First-Class Architectural Design Contraint” INSPEC p. -52-58.
Musoll et al., “Scheduling and Resource Binding for Low Power” 1995 8th International Symposium on System Synthesis p. 104-109.
Seng et al., “Power-Sensitive Multithreaded Architecture” Sep. 2000, p. 17-20.
Aingaran Kathirgamar
Blatt Miriam G.
Gauthier Claude R.
Greenhill David J.
DeCady Albert
Osha & Liang LLP
Stevens Thomas H
Sun Microsystems Inc.
LandOfFree
Data analysis techniques for dynamic power simulation of a CPU does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Data analysis techniques for dynamic power simulation of a CPU, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Data analysis techniques for dynamic power simulation of a CPU will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3957513