Computer graphics processing and selective visual display system – Display driving control circuitry – Controlling the condition of display elements
Patent
1997-10-14
1999-10-12
Downs, Robert W.
Computer graphics processing and selective visual display system
Display driving control circuitry
Controlling the condition of display elements
711150, 711168, 712 35, G06F 945
Patent
active
059661437
ABSTRACT:
Data is allocated into multiple memories with selective variable replication for maximizing performance by minimizing concurrent memory access conflicts. Requirements for concurrent access are summarized in a transformed concurrent access graph. Graph vertices are merged to disallow variable replication. All potential graph merges that cause a reduction in machine cycle time are identified. The ratios of saved cycles/memory cost in bytes are then computed for each potential merge. The potential merges are then sorted by their saved cycles/bytes ratio. Finally, potential merges resulting in replicated variables are selected based on their cycles/bytes ratios until a predefined memory target size is achieved. Either graph coloring or clique partitioning can be used to allocate variables into memory banks.
REFERENCES:
patent: 4571678 (1986-02-01), Chaitin
patent: 5249295 (1993-09-01), Briggs et al.
patent: 5418958 (1995-05-01), Goebel
patent: 5774730 (1998-06-01), Aizikowitz et al.
Briggs-Cooper-Torczon, "Improvements to Graph Coloring Register Allocation," ACM Transactions on Programming Languages and Systems, vol. 16, No. 3, pp. 428-455, May 1994.
Mauricio Breternitz, Jr & John Paul Shen, Implementation Optimization Techniques for Architecture Synthesis of Application-Specific Processors, ACM, Nov. 1991.
Mazen A.R. Saghir, et al., "Automatic Data Partitioning for HLL DSP Compilers", Dept. of Electrical and Computer Engineering, University of Toronto, Canada, pp. 1-6.
Ashok Sudarsanam, et al., "Memory Bank and Register Allocation in Software Synthesis for ASIPs", Department of Electrical Engineering, Princeton University, 5 pgs.
Mauricio Breternitz, et al., "Implementation Optimization Techniques for Architecture Synthesis of Application-Specific Processors", 1991 ACM 0-89791-460-091/0011/0114, pp. 114-123.
Downs Robert W.
Hayden Bruce
Motorola Inc.
Nguyen-Ba Antony
Toler Jeffrey G.
LandOfFree
Data allocation into multiple memories for concurrent access does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Data allocation into multiple memories for concurrent access, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Data allocation into multiple memories for concurrent access will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-657097