Data aligner in reconfigurable computing environment

Details Data aligner in reconfigurable computing environment Data aligner in reconfigurable computing environment

2011-04-05

2011-04-05

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Integrated circuit design processing

Physical design processing

C716S100000, C716S117000

Reexamination Certificate

active

07921396

ABSTRACT:
A data aligner in a reconfigurable computing environment is disclosed. Embodiments employ hardware macros in field configurable gate arrays (FPGAs) to minimize the number of configurable logic blocks (CLBs) needed to shift bytes of data. The alignment mechanism allows flexibility, scalability, configurability, and reduced costs as compared to application specific integrated circuits.

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L. B. Arimilli, et al., Data Alignment Logic Comprising Mux to Mux Stages, IBM Technical Disclosure Bulletin, vol. 38, No. 7, Jul. 1995, pp. 501-504.

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