Data acquisition system using predictive conversion

Details Data acquisition system using predictive conversion Data acquisition system using predictive conversion

2002-05-08

2003-07-08

Young, Brian (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Differential encoder and/or decoder

C341S155000

Reexamination Certificate

active

06590513

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
The technical field of this invention is analog to digital conversion.
BACKGROUND OF THE INVENTION
The majority of conventional analog-to-digital converters (ADC) used in communications applications are self-contained devices that do not take advantage of the structured nature of the signals they convert. They operate essentially open loop and then feed each output data sample to a digital signal processor (DSP) as if these samples were uncorrelated to previous or future samples. These analog-to-digital converters do not take advantage of the highly correlated nature of information signals. This mode of operation is therefore highly inefficient for data transfer and leads to extremely complex design specifications for the converter element.
Conventional analog-to-digital converters have the following characteristics. The structure and predictable behavior of target signals are ignored. The system digital signal processors play a passive role in conventional acquisition processes and thus rely on the open loop performance of the conversion system. The differing silicon fabrication requirements of high performance analog and digital functions are not properly addressed.
FIG. 1
illustrates a fundamental conventional analog-to-digital converter system driving a digital signal processor. An input analog signal
100
is converted to an N-bit binary-weighted digital signal
104
in the analog-to-digital converter
102
. The output stage of the analog-to-digital converter typically contains a first-in-first-out (FIFO) memory
103
that allows for pipelining flexibility. The digital signal processor
105
performs a potentially wide range of processing steps to improve the quality and usefulness of the signal. The N-bit binary interface was developed for a random signal. Typically, the signal to be converted is not at all random, but has a highly predictable behavior.
Feedback has been applied to analog-to-digital converters in some conventional designs. This has been largely in the form of the ‘sigma-delta’ modulator analog-to-digital converter. In this approach, the conversion process focus is on changes in the signal to be converted. A Nyquist sampler is so named because it samples at the Nyquist rate, which is twice the highest frequency component of the input signal. Sigma-delta modulators are over-sampled converters in that they require sampling rates significantly higher than the Nyquist rate.
FIG. 2
illustrates this approach in a basic 1-bit sigma-delta modulator. Analog data input samples X(nT)
200
are processed through an input summing function
202
whose output is integrated by the integrator block
203
. The integrated output is fed to a 1-Bit analog-to-digital converter
204
. The output from
204
forms a digital output signal Y(z)
206
that may be further processed to improve its quality and usefulness. Output
206
is also converted to analog by digital-to-analog converter (DAC)
208
with output
209
forming the subtraction input to summing junction
202
.
The sigma-delta modulator performs the following useful operations. These modulators utilize over-sampling to spread the quantization noise over an increased frequency range. These modulators move and shape quantization noise resulting in an increased portion of in-band noise being moved out-of-band. These modulators use digital decimation filters to remove out-of-band noise and reduce the effective sampling rate at the sigma-delta modulator output.
Sigma-delta modulators have disadvantages that limit their usefulness. When converting signals that change rapidly thus containing high frequency components, sigma-delta modulators must use a high sampling rate to maintain the required level of oversampling. This becomes prohibitive for many applications.
Sigma-delta modulators have been extended in a limited fashion to utilize an N-Bit analog-to-digital converter and digital-to-analog converter, but these are limited to low bit-sizes due to the complexity of implementing multi-bit converters at the required over-sampling ratio. The signal-to-noise ratio of a sigma-delta modulator is a complex function of the over-sampling ratio, the order of the integrator, higher order integrators can push more of the in-band noise out-of-band, and the number of bits in the quantizer and digital-to-analog converter. Sigma-delta modulators must either maintain a given over-sampling ratio which requires very high sampling rates for high-frequency input signals, or increase the order of the integrator which can cause stability problems, or increase the number of bits in the quantizer and digital-to-analog converter which adds complexity (and significant cost) to the design.
SUMMARY OF THE INVENTION
The predictive data acquisition system of this invention comprises an analog-to-digital converter that includes a prediction feedback element in an architecture that is significantly different from conventional analog-to-digital converter systems. The converter uses the computing power of a digital signal processor to exploit the inherent structure of the target signal by predicting the next sample based on pre-defined rules and previous samples.
This digital prediction is converted to an analog signal using a digital-to-analog converter. An analog input summing network and error amplifier compares the predicted signal with the target input signal and creates an error signal. An error encoder translates the error signal into a form that the digital signal processor can understand.
The prediction feedback element contains a prediction core processor and a parameter estimator each having model parameter inputs from a digital signal processor which controls the processing according to the prediction algorithm. The prediction core processor uses the prediction error and output from its parameter estimator to more accurately predict the next sample. A negative feedback loop is thus formed by this system. Careful design of the prediction algorithm can be made to drive the prediction error toward zero. Operating on the relatively small error signal in the forward and feedback paths enhances the conversion performance and data transfer efficiency.


REFERENCES:
patent: 5838272 (1998-11-01), Steiner
patent: 6433723 (2002-08-01), Randall

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