Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion
Reexamination Certificate
2000-11-14
2001-12-25
Young, Brian (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Analog to digital conversion
C341S161000
Reexamination Certificate
active
06333708
ABSTRACT:
The international applications PCT/CH99/00153 (WO99/60495) and PCT/CH99/00154 (WO99/60496), whose contents are hereby incorporated by way of reference, claim priority of the same application EP98810452.7.
FIELD OF THE INVENTION
The present invention concerns a data acquisition system comprising a circuit for converting an input analog signal into a plurality of digital signals. The present invention concerns in particular a data acquisition system comprising a conversion circuit supplying digital signals for processing by a digital processor in a data acquisition system.
RELATED ART
Many types of data acquisition systems are known, for example transitory recorders and digital oscilloscopes, in which it is necessary to convert one or several analog signals into one or several digital signals capable of being stored in a digital memory and processed by a digital processor. These systems comprise generally an input stage constituted of one or several digitizers and of a memory for digitized data; the processor accesses said memory most often through a bus. In low-frequency systems, this memory can for example be constituted directly by the RAM of a computer. The digitized data are stored in this memory and processed, for example displayed, by the processor of this computer either in real time or later, for example when all the data have been acquired.
More and more often in electronic technology, very high frequency analog signals requiring very fast acquisition systems, for example oscilloscopes, are used. Digitizers are currently made that work with a sampling frequency greater than 500 MHz, for example on the order of 1 GHz or more; it is to be predicted that these current limits will be exceeded with the appearance of better performing components. These digitizers permit by virtue of the Nyquist principle to supply an unambiguous digital representation of analog signals having a maximum frequency of several hundred MHz.
These ultra-fast digitizers supply a digital word, for example a byte in the case of eight bit converters, at each flank of the sample signal, for example each nanosecond; the digital output frequency generated is thus extremely high, and generally incompatible with the maximum write access frequency of the usual memory circuits. One thus knows the utilization of demultiplexers, which make it possible in a data acquisition system to supply in parallel N words delivered in series by a digitizer. The output frequency of the demultiplexer is divided by N, at a price of an increase by this same factor of the width of the data bus. The demultiplexer thus allows the requirements as to the speed of memory access to be reduced and several words supplied in series by the digitizer to be delivered in parallel.
FIG. 1
illustrates an example of an embodiment of a demultiplexer with a demultiplexing factor N of 4. It comprises a clock signal generator
20
and the demultiplexer itself.
The clock signal generator
20
comprises a 2 bits counter
200
that counts the ascending and/or descending flanks of the sample signal CK used by the digitizers. The two bits supplied by the counter
200
are converted by the 4-line decoder
201
into four signals CK
1
to CK
4
that are phase-shifted by 90° and whose frequency is 1/N=¼ of that of the sample signal CK.
In the demultiplexer itself, the digital words of m bits supplied by the digitizers to the respective ascending flanks of CK
1
, CK
2
and CK
3
are stored in respective m bits registers
21
,
22
,
23
. At the ascending flank of CK
4
, the word supplied by the digitizer is recorded in the register
27
, and simultaneously the contents of the registers
21
to
23
is copied into the respective registers
24
to
26
; the registers
24
to
27
thus supply in parallel, and until the next ascending flank of CK
4
, N=4 words delivered in series by the digitizer. The demultiplexer
2
thus allows a stream of words of m bits to be converted into another stream of words of N×m bits with an output frequency N times weaker, and thus compatible with the writing speeds of available memory components.
When the stream of data to be analyzed is continuous, or very long, it is not possible to store it entirely in a memory at an acceptable cost: it is thus necessary for the digital processor to access the data stored by the digitizer in real time. The processing of the stored data can comprise a large number of different operations according to the application, for example an error check, a detection of minima and of maxima, a storage in a permanent memory and a display on a monitor for example.
The external input frequencies of current digital processors are comparable to the maximum output frequencies of the aforementioned digitizers. In the particular case where these frequencies are equal, and if the demultiplexer factor N equals four, the digital processor has only four cycles to access four stored words and to process these four words. Therefore only relatively simple processing operations can be effected in real time. A choice of demultiplexing factor N greater than four requires an increase of the width of the storing memory as well as of the microprocessor's data bus, and thus causes an important increase of the costs.
A purpose of the present invention is to remedy these inconveniences and to extend the possibilities of real-time processing and analyzing of high-frequency digital data in a data acquisition system.
BRIEF SUMMARY OF THE INVENTION
According to the invention, these purposes are achieved by means of a data acquisition system comprising a circuit for converting a high-frequency analog input signal into a plurality of digital signals for processing by a digital processing system including at least one digital processor comprising a real-time digital processing circuit for processing in real time data delivered by the demultiplexer, for processing data during their storage and supplying processed results to said digital processor.
This real-time digital processing circuit processes directly the digital data available at the output of the demultiplexer and supplies results to the digital processor, for example additional signals or data derived from the multiplexer's data. The digital processor in this manner is freed from the data processing operations that can be effected by real-time processing means.
Advantageously, the operation parameters of the real-time digital processing circuit can be defined with parameters or even completely determined or programmed by the digital processor; a great flexibility is thus achieved, and it is possible to effect a different processing according to the application without modifying the physical configuration of the circuit.
U.S. Pat. No. 5,526,301 describes a data acquisition system comprising a sampler and analog processing means of the sampled signal. This document however concerns a purely analog processing circuit; no memory or storing element is further provided for storing the sampled signal.
REFERENCES:
patent: 5397981 (1995-03-01), Wiggers
patent: 5428357 (1995-06-01), Haab et al.
patent: 5557800 (1996-09-01), Kasimov et al.
patent: 5856800 (1999-01-01), Le Pailleur
patent: 6166673 (2000-12-01), Odom
patent: 0 629 966 A1 (1994-12-01), None
Hungerbuehler Viktor M.
Mauron Bernard
Acquiris
Pearne & Gordon LLP
Young Brian
LandOfFree
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