Data access device for DRAM

Details Data access device for DRAM Data access device for DRAM

1997-09-12

2000-07-18

Chan, Eddie P.

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

36518908, 365203, G11C 800, G11C 700

Patent

active

060916613

ABSTRACT:
The data access device of a dynamic random access memory includes a plurality of bit line sensing amplifiers, decoders, and column sensing amplifiers. The plurality of bit line sensing amplifiers amplify a data signal and inverted data signal applied to a bit line and inverted bit line, respectively. The plurality of decoders each receive an inverted pulse signal and an associated code signal. Each decoder generates an enable signal based on the inverted pulse signal and the associated code signal. Each decoder includes a first and second NMOS transistor. Each of the column sensing amplifiers is associated with one of the decoders and one of the bit line sensing amplifiers, and each of the column sensing amplifiers selectively loads the data signal and inverted data signal of the associated bit line sensing amplifier on a first and second data bus, respectively, based on the enable signal from the associated decoder. Each column sensing amplifier includes a third and fourth NMOS transistor. A data amplifier connected to the first and second data buses amplifies the data signal and the inverted data signal loaded thereon.

REFERENCES:
patent: 5274598 (1993-12-01), Fujii et al.
patent: 5392242 (1995-02-01), Koike
patent: 5574681 (1996-11-01), Foss et al.
patent: 5631865 (1997-05-01), Iwase et al.

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