Data access apparatus for preventing further cache access in cas

Details Data access apparatus for preventing further cache access in cas Data access apparatus for preventing further cache access in cas

1995-05-31

1996-08-06

Gossage, Glenn

Boots, shoes, and leggings

395479, 395490, 39518203, 39518318, 364DIG1, 36424341, 3642543, 3642653, 3642663, 36494492, 3649456, 3649571, 3649642, 371 401, 371 511, G06F 1300, G06F 1100

Patent

active

055443419

ABSTRACT:
A data processor and method for preventing access to a cache memory when an abnormality occurs during a block data transfer. The data processor is provided with a central processing unit (CPU), a memory and the cache which stores a part of the data being stored in the memory. When the data to be accessed by the central processing unit is not stored in the cache, the data processor employs a block transfer method where the central processing unit reads out from the memory a block of data, including a predetermined number of data (words) in which the data to be accessed is located. When an abnormality, such as a parity error, is detected in transferring a data word in the block of data to be accessed, the cache is inhibited from reading another data word in the block to be accessed, and the CPU stops reading out the rest of the block of data to be read out from the memory, so that the central processing unit can immediately take action to respond to the abnormality.

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