Patent
1979-03-28
1981-09-08
Wojciechowicz, Edward J.
357 49, 357 55, 357 56, 357 86, H01L 2702
Patent
active
042888077
ABSTRACT:
In a Darlington circuit with integrated speed-up diode the parasitic four-layer effect (p-n-p-n), which is detrimental to the circuit, is removed by giving the diode a divided configuration. The width of the sub-regions is chosen to be so small that the short-circuited p-n junction between the cathode of the diode and the base of the control transistor cannot or substantially can not be biased in the forward direction in the inner part of the semiconductor device.
REFERENCES:
patent: 4138690 (1979-02-01), Nawa et al.
IBM-Tech. Bul.-vol. 16, No. 6, Nov. 1973-pp. 1735-1736 Jones et al.
Enzlin Theodoor H.
Janssen Antonius J.
Biren Steven R.
Briody Thomas A.
Mayer Robert T.
U.S. Philips Corporation
Wojciechowicz Edward J.
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