Dark current and lag reduction

Details Dark current and lag reduction Dark current and lag reduction

2008-03-24

2010-11-16

Epps, Georgia Y (Department: 2878)

Radiant energy

Photocells; circuits and apparatus

Photocell controlled circuit

C250S208100, C348S308000

Reexamination Certificate

active

07834306

ABSTRACT:
The claimed subject matter provides systems and/or methods that facilitate reducing dark current and lag in a CMOS imaging System-on-Chip (iSoC) sensor. For instance, a vertical output driver can output a signal upon a node connected to gates of reset transistors and/or gates of transfer transistors of pixels in the pixel array while operating in rolling shutter mode and/or global shutter mode. Further, a pre-charger can transition a voltage of the node to a first voltage level. Moreover, a booster can further adjust the voltage of the node from the first voltage level to a second voltage level. The booster can have variable drive capability that enables varying operation thereof according to at least one degree of freedom (e.g., speed of the booster proceeding to the second voltage level, frequency of yielding charge to the node, the second voltage level, or timing of the booster and the pre-charger, . . . ).

REFERENCES:
patent: 6297687 (2001-10-01), Sugimura
patent: 7110038 (2006-09-01), Watanabe et al.
patent: 7397020 (2008-07-01), Roh
patent: 2008/0074519 (2008-03-01), Rysinski et al.

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