Dangerous range detector for floating point adder

Details Dangerous range detector for floating point adder Dangerous range detector for floating point adder

1989-11-20

1992-04-07

Shaw, Dale M.

Boots, shoes, and leggings

36471504, G06F 738

Patent

active

051034182

ABSTRACT:
A floating point adder operates in a subtraction mode. In order to avoid excess shifting resulting in a negative exponent, as might happen in the case of a substraction operation which results in an unnormalized number where the exponent of the subtraction result is low, the following steps are provided. A number is created having leading zeros no greater in number than the value of the exponent part; this number is logically combined with the mantissa part in a bit-wise OR operation, to provide a combined number; the position of a leading bit state of the combined number is detected, and the mantissa part of the original number is shifted a number of bit positions dependent on the detected position.

REFERENCES:
patent: 4562553 (1985-12-01), Mattedi et al.
patent: 4644490 (1987-02-01), Kobayashi et al.
patent: 4785421 (1988-11-01), Takahashi et al.

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