Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material
Reexamination Certificate
2000-12-06
2003-09-23
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
C438S637000, C438S638000, C438S786000, C438S778000, C257S639000, C257S635000, C257S636000, C257S640000
Reexamination Certificate
active
06624053
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to integrated circuits, and, more particularly, to a damascene-type interconnection structure.
BACKGROUND OF THE INVENTION
The interconnection structures of integrated circuits typically include aluminum doped with copper (Al—Cu), where the doping level is approximately 2 to 4%. The process used for producing these interconnection structures includes depositing the metal, etching the metal to form the interconnection network, and depositing a dielectric thereon for insulating the metal lines both laterally (interline insulation) and vertically (interlevel insulation). This process is commonly involves filling the interline spaces with the dielectric.
In order to improve performance characteristics (e.g., increased speed, lower consumption) it is necessary to use more conductive metals and lower permittivity materials. For metallization purposes, copper (which has a resistivity roughly two times lower than Al—Cu) proves to be a good candidate. Yet, the use of copper may be problematic in a conventional structure because it is very difficult to etch. This is why copper is used in a so-called damascene structure. In a damascene structure, the network of interconnections is formed by etching trenches in a very low permittivity dielectric, depositing a metal nitride barrier layer, and filling the trenches with copper. The excess copper and barrier material are then eliminated by polishing to leave only the dielectric between the metal lines. The production of such a structure requires the use of dielectric material interface layers with hard masks, and copper diffusion barrier or stop layers for mechanochemical polishing (CMP).
Dielectric interface materials such as SiO
2
, Si
3
N
4
and SiO
x
N
y
are conveniently used in damascene structures because they are widely used in the production of integrated circuits. They may be used either in an active zone of the circuits as insulators or at the interconnection level as intermetallic dielectrics or passivation dielectrics. These materials may be deposited by various well known methods, e.g. by thermal oxide growth, low pressure chemical vapor deposition CVD (LPCVD), atmospheric CVD (APCVD), or plasma assisted CVD (PECVD), as will be appreciated by those of skill in the art.
The required properties for dielectric interface materials in damascene structures are as follows. The materials used for the barrier must have a good resistance to the diffusion of copper. The materials used as a hard mask must have good etching selectivity with respect to the underlying materials of the organic or mineral type. Additionally, the materials used as a barrier layer to polishing must have a good resistance to chemo-mechanical polishing in order to permit the elimination of the excess copper above the lines without deterioration of the dielectric. In other words, these materials must have a high polishing selectivity with respect to copper. Furthermore, these materials must also have good electrical strength characteristics, namely a low dielectric constant and low leakage current. Also, the materials deposited directly on the very low permittivity dielectrics (i.e., the materials of the hard masks and barrier layers) must have good chemical compatibility with these dielectrics.
Among the conventional dielectric interface materials, SiO
2
has good electrical properties and a good etching selectivity with respect to organic materials. Even so, its properties are inadequate in other respects. Si
3
N
4
has a good etching selectivity, a good abrasion resistance, and a good resistance to the diffusion of copper, but its dielectric constant is high. SiON provides intermediate characteristics between those of Si
3
N
4
and SiO
2
. Thus, none of these conventional materials exhibits all the desired properties.
In addition, certain of these dielectric interface materials deposited by PECVD, for example, from oxidizing gases (e.g., O
2
, N
2
O, NO
2
, O
3
) can induce an oxidation of the interface or the entire matrix of the low permittivity material. As a result, properties such as dielectric constant, leakage current, densification with thickness modification, adhesion loss and chemical modification may deteriorate. Dielectric materials with a very low permittivity based on Si—O, a porous structure, and having carbon radicals (of the Si—R type) or hydrides (of the Si—H type) are particularly affected by these deteriorations. Thus, for such materials, during the deposition of the dielectric interface material layer there is an oxidation of a depth varying as a function of the porosity thereof. This oxidation induces the formation of silanol (Si—OH) and water, which are respectively very polar radicals or molecules.
Accordingly, finding dielectric materials for use in producing interface layers that satisfy the above-noted properties is problematic.
SUMMARY OF THE INVENTION
The invention makes it possible to produce structures of the damascene type using dielectrics having a very low permittivity of the Si—O based mineral type having a porous structure. These very low permittivity dielectrics incorporate organic radicals (e.g. Si—CH
3
) or hydrides (e.g. Si—H). The dielectrics may be xerogels, aerogels of methyl or silsesquioxane hydrogen, or any other material based on a porous mineral oxide which can incorporate organic radicals obtained by the spreading of a precursor or by a CVD process. The dielectric interface layers are formed by a combination of SiOCH and SiCH layers or sublayers.
According to the invention, a method for making a damascene-type interconnection structure adjacent a surface of a microelectronic device includes depositing a first dielectric material layer adjacent the surface and depositing a first dielectric material interface layer on the dielectric material layer. The first dielectric material interface layer is deposited by depositing a first SiCH layer on the dielectric layer and depositing a first SiOCH layer on the SiCH layer. At least one interconnection is formed within the first dielectric material layer to contact the surface, and the first dielectric material layer provides a housing for the at least one interconnection.
The first dielectric material layer may include a very low permittivity dielectric material of a mineral type based on Si—O and having at least one of an organic radical or a hydride. The method may also include depositing a second dielectric material layer on the first dielectric material interface layer and depositing a second dielectric material interface layer on the second dielectric layer. The second dielectric material interface layer may be deposited by depositing a second SiCH layer on the second dielectric material layer and depositing a second SiOCH layer on the second SiCH layer. Depositing the second dielectric material interface layer may also include depositing a third SiCH layer on the second SiOCH layer.
Forming the at least one interconnection may include forming at least one copper interconnection, and a metal layer may be deposited adjacent the first dielectric material layer prior to forming the at least one copper interconnection to reduce diffusion of copper into the first dielectric material layer. The microelectronic device may be formed on a silicon substrate, for example. Furthermore, forming the at least one interconnection may include etching at least one hole in the first SiOCH layer, etching portions of the first SiCH layer, the first dielectric material interface layer, and the first dielectric material layer beneath the at least one hole using the first SiOCH layer as an etching mask to thereby form at least one trench. Copper may then be deposited within the at least one trench to thereby form the at least one interconnection. A barrier layer may be deposited in the trench prior to depositing the copper to reduce diffusion of the copper into the first dielectric material layer.
According to an alternative embodiment, a method for making a dual damascene-type interconnection structure on a surface of a semiconductor substr
Allen Dyer Doppelt Milbrath & Gilchrist, P.A.
Anya Igwe U.
STMicroelectronics S.A.
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