Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
2000-09-21
2004-02-10
Lee, Eddie (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S751000
Reexamination Certificate
active
06690091
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to fabrication of a semiconductor device and more particularly to a method and structure for forming a damascene structure with reduced capacitance by using carbon nitride, boron nitride, or boron carbon nitride to form a low-K passivation layer, etch stop layer, and/or cap layer.
2. Description of the Prior Art
As semiconductor dimensions continue to shrink and device density continues to increase, capacitance between conductive structures becomes increasingly important. With a smaller amount of dielectric material separating conductive structures, the dielectric constant must be increased to provide the same capacitance. However, materials for a passivation layer, an etch stop layer, and a cap layer are typically chosen for their etch selectivity properties.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering the following patents.
U.S. Pat. No. 5,834,845 (Stolmeijer) shows a damascene interconnect method which discloses a BN etch stop layer, but states that a silicon nitride etch stop layer is preferred. This invention does not show a passivation layer or a cap layer, nor does it disclose any method for forming a BN etch stop layer.
U.S. Pat. No. 5,821,169 (Nguyen et al.) shows a dual damascene process with a hard mask (cap layer) material selected from a group of insulating materials including BN. This invention teaches that the hard mask material should be selected for etch selectivity to the inter level dielectric layer, and does not disclose any method for forming a BN hard mask layer.
U.S. Pat. No. 5,904,565 (Nguyen et al.) shows a dual damascene process with various cap, etch stop, and barrier layers.
U.S. Pat. No. 5,708,559 (Brabozon et al.) teaches a damascene capacitor process with a dielectric layer of BN.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method for forming a damascene structure with reduced capacitance.
It is another object of the present invention to provide a method for forming a damascene structure with reduced capacitance using passivation layer, etch stop layer and/or cap layer comprising carbon nitride, boron nitride, or boron carbon nitride.
It is another object of the present invention to provide a method for forming a passivation layer, an etch stop layer, and/or a cap layer using materials having a low dielectric constant (≈3) which is compatible with existing semiconductor fabrication processes and equipment.
It is yet another object of the present invention to provide a damascene structure with reduced capacitance using passivation layer, etch stop layer and/or cap layer comprising carbon nitride, boron nitride, or boron carbon nitride.
To accomplish the above objectives, the present invention provides a method for forming a damascene structure with reduced capacitance by forming one or more of: the passivation layer, the etch stop layer, and the cap layer using a low dielectric constant material comprising carbon nitride, boron nitride, or boron carbon nitride. The method begins by providing a semiconductor structure having a first conductive layer thereover. A passivation layer is formed on the first conductive layer. A first dielectric layer is formed over the passivation layer, and an etch stop layer is formed over the first dielectric layer. A second dielectric layer is formed over the etch stop layer, and an optional cap layer can be formed over the second dielectric layer. The cap layer, the second dielectric layer, the etch stop layer, and the first dielectric layer are patterned to form a via opening stopping on said passivation layer and a trench opening stopping on said etch stop layer. A carbon nitride passivation layer, etch stop layer, or cap layer can be formed by magnetron sputtering from a graphite target in a nitrogen atmosphere. A boron nitride passivation layer, etch stop layer, or cap layer can be formed by PECVD using B
2
H
6
, ammonia, and nitrogen. A boron carbon nitride passivation layer, etch stop layer, or cap layer can be formed by magnetron sputtering from a graphite target in a nitrogen and B
2
H
6
atmosphere.
The present invention provides considerable improvement over the prior art. One or more of: the passivation layer, the etch stop layer, and the cap layer can be formed comprising carbon nitride or carbon boron nitride using a magnetron sputtering process, or comprising boron nitride using a PECVD process. The invention therefore provides a method of forming a damascene structure with a reduced capacitance by allowing one or more layers to be formed using a material having a low dielectric constant using existing equipment and process. Also, by selecting which layers are formed using a low dielectric constant material, the present invention provides a method for forming a damascene structure which optimizes performance, reliability and fabrication cost.
The present invention achieves these benefits in the context of known process technology. However, a further understanding of the nature and advantages of the present invention may be realized by reference to the latter portions of the specification and attached drawings.
REFERENCES:
patent: 5708559 (1998-01-01), Brabazon et al.
patent: 5739579 (1998-04-01), Chiang et al.
patent: 5821169 (1998-10-01), Nguyen et al.
patent: 5834845 (1998-11-01), Stolmeijer
patent: 5856706 (1999-01-01), Lee
patent: 5904565 (1999-05-01), Nguyen et al.
patent: 6083822 (2000-07-01), Lee
patent: 6144099 (2000-11-01), Lopatin et al.
patent: 6218302 (2001-04-01), Braeckelmann et al.
patent: 6232235 (2001-05-01), Cave et al.
patent: 6316359 (2001-11-01), Simpson
patent: 6352940 (2002-03-01), Seshan et al.
patent: 6358842 (2002-03-01), Zhou et al.
patent: 6372636 (2002-04-01), Chooi et al.
patent: 6376353 (2002-04-01), Zhou et al.
Chooi Simon
Xu Yi
Zhou Mei Sheng
Lee Eddie
Owens Douglas W.
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