Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2007-01-02
2007-01-02
Vinh, Lan (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S624000, C438S638000, C438S706000
Reexamination Certificate
active
10746420
ABSTRACT:
A damascene process using a doped and undoped oxide ILD is described. The selectivity between the carbon doped and carbon free oxide provides an etching stop between the ILD's in addition to providing mechanical strength to the structure.
REFERENCES:
patent: 6165898 (2000-12-01), Jang et al.
patent: 6251770 (2001-06-01), Uglow et al.
patent: 6287955 (2001-09-01), Wang et al.
patent: 6395632 (2002-05-01), Farrar
patent: 6911397 (2005-06-01), Jun et al.
patent: 2002/0173143 (2002-11-01), Lee et al.
patent: 2003/0001240 (2003-01-01), Whitehair et al.
patent: 2003/0064580 (2003-04-01), Ott et al.
patent: 2003/0207561 (2003-11-01), Dubin et al.
patent: 2004/0056366 (2004-03-01), Maiz et al.
patent: 2005/0032355 (2005-02-01), Yeh et al.
PCT Int'l Search Report, PCT/US2004/043653, dated Apr. 11, 2005, 3 pages.
Andideh, E. Scheran, et al., “Interfacial adhesion of copper-low k interconnects,” Interconnect Technology Conference, 2001. Proceedings of the IEEE 2001 Int'l, found at: http://ieeeexplore.ieee.org/xpls/absprintf.jsp?arnumber=930077, 1 pg.
Bohr Mark
Dubin Valery M.
Hussein Makarem A.
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Vinh Lan
LandOfFree
Damascene process for fabricating interconnect layers in an... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Damascene process for fabricating interconnect layers in an..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Damascene process for fabricating interconnect layers in an... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3722113