Damascene process at semiconductor substrate level

Details Damascene process at semiconductor substrate level Damascene process at semiconductor substrate level

2006-02-17

2008-08-19

Potter, Roy K (Department: 2822)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C438S715000

Reexamination Certificate

active

07413991

ABSTRACT:
A damascene structure and process at semiconductor substrate level. A pre-metal dielectric layer is provided on a semiconductor substrate with an opening exposing a contact region on the substrate. A buffer metal layer is provided on the exposed contact region, and a barrier layer is provided on the interior of the opening. A conductor is provided on the buffer metal layer, substantially filling the opening to electrically connect to the contact region.

REFERENCES:
patent: 5856226 (1999-01-01), Wu
patent: 6211085 (2001-04-01), Liu
patent: 6309977 (2001-10-01), Ting et al.
patent: 541651 (1991-06-01), None
Taiwan Patent Office Action

Affiliated with

Also associated with

Rating

Damascene process at semiconductor substrate level does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Damascene process at semiconductor substrate level, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Damascene process at semiconductor substrate level will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3999579