Damascene interconnect with bi-layer capping film

Details Damascene interconnect with bi-layer capping film Damascene interconnect with bi-layer capping film

2005-03-29

2005-03-29

Smith, Matthew (Department: 2825)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Chip mounted on chip

C257S774000

Reexamination Certificate

active

06873057

ABSTRACT:
A damascene interconnect structure with a bi-layer capping film is provided. The damascene interconnect structure comprises a semiconductor layer and a dielectric layer disposed on the semiconductor layer. The dielectric layer has a main surface and at least one damascened recess provided on the main surface. A copper wire is embedded in the damascened recess. The copper wire has a chemical mechanical polished upper surface, which is substantially co-planar with the main surface of the dielectric layer. After polishing the upper surface of the copper wire, the upper surface is pre-treated and reduced in a conductive plasma environment at a temperature of below 300° C. A bi-layer capping film is thereafter disposed on the upper surface of the copper wire. The bi-layer capping film consists of a lower HDPCVD silicon nitride layer and an upper doped silicon carbide layer.

REFERENCES:
patent: 6147009 (2000-11-01), Grill et al.
patent: 6566242 (2003-05-01), Adams et al.
patent: 6649531 (2003-11-01), Cote et al.
patent: 6656840 (2003-12-01), Rajagopalan et al.
patent: 6737747 (2004-05-01), Barth et al.
patent: 20040173907 (2004-09-01), Chen et al.

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