Damascene gate semiconductor processing with local thinning...

Details Damascene gate semiconductor processing with local thinning... Damascene gate semiconductor processing with local thinning...

2005-11-22

2005-11-22

Nhu, David (Department: 2818)

Semiconductor device manufacturing: process

Chemical etching

Liquid phase etching

C438S933000, C438S752000

Reexamination Certificate

active

06967175

ABSTRACT:
A method of manufacturing a semiconductor device may include forming a fin on an insulator and forming a gate oxide on sides of the fin. The method may also include forming a gate structure over the fin and the gate oxide and forming a dielectric layer adjacent the gate structure. Material in the gate structure may be removed to define a gate recess. A width of a portion of the fin below the gate recess may be reduced, and a metal gate may be formed in the gate recess.

REFERENCES:
patent: 6225173 (2001-05-01), Yu
patent: 6413802 (2002-07-01), Hu et al.
patent: 6472258 (2002-10-01), Adkisson et al.
patent: 6475869 (2002-11-01), Yu
patent: 6475890 (2002-11-01), Yu
patent: 6583469 (2003-06-01), Fried et al.
patent: 6642090 (2003-11-01), Fried et al.
patent: 6787854 (2004-09-01), Yang et al.
patent: 6855989 (2005-02-01), Wang et al.
patent: 2002/0093053 (2002-07-01), Chan et al.
patent: 2002/0130354 (2002-09-01), Sekigawa et al.
patent: 2002/0153587 (2002-10-01), Adkisson et al.
patent: 2002/0177263 (2002-11-01), Hanafi et al.
patent: WO 04/068589 (2004-08-01), None
patent: WO 04/093181 (2004-10-01), None
Co-pending U.S. Appl. No. 10/405,342, filed Apr. 3, 2003 entitled: “Method for Forming a Gate in a FinFet Device and Thinning a Fin in a Channel Region of the FinFet Device,” 17 pages specification; 14 sheet of drawings.
Digh Hisamoto et al.: “FinFET—Self-Aligned Double-Gate MOSFET Scalable to 20 nm,” IEEE Transactions on Electron Devices, vol. 47, No. 12, Dec. 2000, pp. 2320-2325.
Yang-Kyu Choi et al.: “Sub-20nm CMOS Fin FET Technologies,” 2001 IEEE, IEDM, pp. 421-424.
Xuejue Huang et al.: “Sub-50 nm P-Channel Fin FET,” IEEE Transactions on Electron Devices, vol. 48, No. 5, May 2001, pp. 880-886.
Yamg-Kyu Choi et al.: “Nanoscale CMOS Spacer FinFET for the Terabit Era,” IEEE Electron Device Letters, vol. 23, No. 1, Jan. 2002, pp. 25-27.
Xuejue Huang et al.: “Sub 50-nm FinFET: PMOS,” 1999 IEEE, IEDM, pp. 67-70.
Co-pending U.S. Appl. No. 10/754,540, filed Jan. 12, 2004; entitled: “Narrow-Body Damascene Tri-Gate FinFET,” 13 page specification, 13 sheets of drawings.

Affiliated with

Also associated with

Rating

Damascene gate semiconductor processing with local thinning... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Damascene gate semiconductor processing with local thinning..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Damascene gate semiconductor processing with local thinning... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3494480