Coded data generation or conversion – Analog to or from digital conversion – Digital to analog conversion
Reexamination Certificate
1999-02-09
2002-02-26
Young, Brian (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Digital to analog conversion
Reexamination Certificate
active
06351230
ABSTRACT:
BACKGROUND OF THE INVENTION
Solid-state Electronic Computer Communication involves accurately acquiring and converting digital data elements into unique analog symbols and back again from analog into Digital Data correctly, from locations near or far (CPU & Memory) on or off motherboard by one wire above ground at low cost and at very high frequencies/super high frequencies (VHF/SHF). The transfer of data in bytes per second for the subject device is 4 mega bytes at 100% correct stored data. This is for copper wire systems and much greater speeds are obtainable when used in other application formats, e.g. wireless, microwave, radio telemetry, laser, laser diodes, light emitting diodes and any other form of RF carrier conduit.
The state of the art in computer communications, known as Baud Rates, was 300, 600. 900, and 1200, with greater speed ascertainable beyond 4800 bits per second. These Baud Rates were slowing the computer and still do today. The Federal Communication Commission (FCC) was being disagreeable about the use of bits as an atom element. The FCC perceived that a bit was not an intelligible part of communication operations. It also contended that a bit was not another form of a character or a symbol. A serial bit stream could be used to form a character or symbol, being an intelligible element, when considered as a single pattern. In the truest meaning, it does take 5, 6, 7 or more bits to represent any one character for the human intellect to perceive. The same is not true for all intellects such as created for computing machines, called digital-logic. Many computers do have sensing arrays that may need only a single bit, {to be on or off}, in order to know or sense the correctness for proper operation.
QUAD Ltd. of the United Kingdom being patented in 1967 under the English patent standards. They nicknamed this predecessor circuit, “current dumping”. In terms of engineering it was called ‘FEED FORWARD CURRENT’. Under QUAD style of this circuit, it performed faithfully for signwaves right out to 200 cps and trianglewave at approximately one-half that frequency, although, squarewaves brought in 12.5 k cycles per second as a maximum frequency. The state of technology throughout the thirty years had not improved the above characteristic even into extremely low resistance, for example less than one ohm, at multiply reactive component impedance (multiply reactive is any value of both compactive and inductive reactants). This largely makes the usefulness of current dumping relevant only to the audio frequency bandwidth, and even not when required to do squarewaves in audio sounds.
‘FEED FORWARD CURRENT CIRCUITRY’ was introduced in mid year of 1998 by Analog Devices Inc. They have developed this circuitry into moderately high frequency, “VHF”, operational amplifiers which notable are able to handle signals that cause the output wave form to come within {fraction (2/10)} of a volt of both positive and negative power supply voltages, while managing a noise of is {fraction (1/1,000,000)} the level of the output signal.
Previous beta configuration transistor circuits have a flaw that causes the gain of the circuit to roll off inversely proportional to the frequency. Due to the inherent capacitance of the collector to base reverse bias diode junction. Although, this capacitance is offset by the inherent capacitance of the forward bias diode comprised by the base to the emitter junction, being made somewhat a smaller value by this second diode in relationship to the ‘hfe of the transistor. This is because of it's inversely proportioned by the gain know as the ‘hfe’ of the transistor. In the beta configuration, the collector circuit is always 180 degrees out of phase with respect to the input signwave. The emitter circuit is in phase with respect to the signwave. Under Ohm's Law capacity reactives, is inversely proportional to the frequency. Therefore, as the frequency rises within a transistor beta configuration circuit, the output signal is shunted into the input signal at values that are inversely proportional to the frequency. Thereby being added together with ([C of cb, plus {C of be and C of 1/cb}] times “hfe”). This causes a real gain roll off and therefore, the transistor effectively does not amplify after a certain limit. This is know as alpha cut off. In summing up, beta configurated transistors, radio waves used from the VHF spectrum and through out near light RF spectrum, require very special and costly semi-conductor designed and manufacturing processes. Please refer to ‘Old Beta’ Diagram (FIG.
5
).
BRIEF SUMMARY OF THE INVENTION
The subject invention relates to a device utilizing common market digital to analog converter and analog to digital converter which has to be excessively tuned to make up for the inherent inaccuracies that the DAC into ADC in order to get correct conversion of digital to analog and this analog back into correct digital parallel bit pattern. This DACTRANS MATCHCADO utilizes feed forward current and multiply phase modulation of the carrier as a means to recognize the correct bit states. The DAC CADO units interpose for the DAC ADC causes the unit to be simpler in tuning and the feed forward current makes the buffer oscillators have true and correct Signwave values.
To best understand and envision this process within the mind, we will relate the analog carrier wave form as a symbol to the constellations. Like the Orion constellation plotting the peaks of wave forms on a two dimensional graph, having ‘x’ and ‘y’ axis, with point rather than wave lines, makes this appear as if you were looking at a star chart. The ‘x’ represents relative amplitude and the ‘y’ axis represents relative degrees within each character dimension. Looking at the explanation of functionality for a 33.6 k bit modem through 56.7 k bit modem, they are to be compared by array of bit points as constellations.
These peripherals now look at these bit-points one at a time. For example, Alpha Ursa Major is the most Northern star going North to South and Beta Ursa Major is second, to state a few, however, when we study the constellations we are looking at them individually, not as a group. The subject device looks at all the bit-points, as one individual consecutively, much the same way we humans look at the star constellations. Examples of this is Cassia Oppia is running from Dracos, who is trying to eat her, as he pours out of the ‘Big Dipper’ {know as Ursa (Bear) major} while she is trying to run around the ‘Little Dipper’ {know as Ursa (Bear) minor}. However, when we look up at these we see the ‘Big Dipper and the ‘Little Dipper’ as a whole.
To further explain the difference between how the subject device uses the resources available to how the existing devices use the system, we will go back to the examples of the constellations. When studying the stars, we use a telescope to see the individual stars we do not require the use of a telescope, to enjoy the view. In the same way, the existing devices require the use of the Central Processing Unit to evaluate the individual points and my device does not use the CPU or other system resources for this evaluation.
The development of this communication device came about in many stages. The first was to setup true and correction elements for the most known character symbols and being able to duplicate all possible symbols correctly. Taking lead from Intel, Texas Instruments (TI), and then later Motorola, the subject invention utilizes simple sub-circuits for each of the bits allowing them to link in a daisy chain fashion. These daisy chain links are based on the examples of the so-called half byte (Hex) processor, which would link with other Hex processor unit(s) forming a (whole) byte, word, and double byte, etc processor's. Such are these functioning machines as 8 bit computer, 16 bit computer, etc. Linking these machines can provide almost unlimited number of bits per data element. The latest example of various parallel-bit wise data elements are 32, 64, and 128
Saliwanchik Lloyd & Saliwanchik
Young Brian
LandOfFree
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