Coded data generation or conversion – Analog to or from digital conversion – Digital to analog conversion
Reexamination Certificate
2011-06-21
2011-06-21
Nguyen, Linh V (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Digital to analog conversion
C341S118000, C341S119000, C341S145000, C341S153000
Reexamination Certificate
active
07965212
ABSTRACT:
Techniques are disclosed for improving the dynamic performance of digital-to-analog converters (DAC), by compensating for the unique delay characteristics of each bit in the DAC summing junction to equalize the delays. In one example case, a DAC device is provided that includes a plurality of current sources and a plurality of switches, each switch operatively coupled between a corresponding one of the current sources and a summing junction that is operatively coupled to an analog output. The device further includes a plurality of switch control lines configured to receive a digital input, each switch control line for controlling a corresponding one of the switches. The device further includes a plurality of compensation delay elements, each associated with a corresponding one of the switch control lines and providing a different delay value.
REFERENCES:
patent: 2827233 (1958-03-01), Johnson et al.
patent: 4405916 (1983-09-01), Hornak et al.
patent: 4751497 (1988-06-01), Torii
patent: 6198419 (2001-03-01), Wen
patent: 6331830 (2001-12-01), Song et al.
patent: 6906652 (2005-06-01), Bugeja
patent: 6992609 (2006-01-01), Zelenin et al.
patent: 7256720 (2007-08-01), Fukuda
patent: 7342528 (2008-03-01), Ng et al.
patent: 7528754 (2009-05-01), Bakkaloglu et al.
patent: 7542812 (2009-06-01), Stroili et al.
patent: 7565392 (2009-07-01), Turner
Manandhar et al, A 20-GHz and 46-GHz, 32x6-bit ROM for DDS Application in InP DHBT Technology, IEEE, 2006, pp. 1003-1006.
Manandhar et al, 36-GHz, 16x6-Bit ROM in InP DHBT Technology Suitable for DDS Application, IEEE Journal of Solid-State Circuits, Feb. 2007, pp. 451-456, vol. 42, No. 2.
Murphy et al., All About Direct Digital Synthesis, Analog Dialogue 38-08, Aug. 2004, pp. 1-5, http://www.analog.com/analogdialogue.
Semiconductor device fabrication, Wikipedia, Feb. 8, 2010, pp. 1-7, http://en.wikipedia.org/wiki/Semiconductor—device—fabrication.
Turner et al, 4-Bit Adder-Accumulator at 41-GHz Clock Frequency in InP DHBT Technology, IEEE Microwave and Wireless Components Letters, Mar. 2005, pp. 144-146, vol. 15, No. 3.
Turner et al., Benchmark Results for High-Speed 4-bit Accumulators Implemented in Indium Phosphide DHBT Technology, IEEE Lester Eastman Conference on High Performance Devices, Rensselaer Polytechnic Institute, Aug. 4-6, 2004, pp. 1-16.
Turner et al., Direct Digital Synthesizer With ROM-Less Architecture at 13-GHz Clock Frequency in InP DHBT Technology, IEEE Microwave and Wireless Components Letters, May 2006, pp. 296-298, vol. 16, No. 5.
Turner et al., Direct Digital Synthesizer With Sine-Weighted DAC at 32-GHz Clock Frequency in InP DHBT Technology, IEEE Journal of Solid-State Circuits, Oct. 2006, pp. 2284-2290, vol. 41, No. 10.
Turner, Steven Eugene, High-Speed Digital and Mixed-Signal Components for X- and KU-Band Direct Digital Synthesizers in Indium Phosphide DHBT Technology, A Thesis, May 2006, 172 pages.
Turner et al., ROM-Based Direct Digital Synthesizer at 24 GHz Clock Frequency in InP DHBT Technology, IEEE Microwave and Wireless Components Letters, Aug. 2008, pp. 566-568, vol. 18, No. 8.
BAE Systems Information and Electronic Systems Integration Inc.
Maloney Neil F.
Nguyen Linh V
LandOfFree
DAC circuit using summing junction delay compensation does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with DAC circuit using summing junction delay compensation, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and DAC circuit using summing junction delay compensation will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2720829