DAC cell circuit

Details DAC cell circuit DAC cell circuit

2005-01-18

2005-01-18

Williams, Howard L. (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

With particular solid state devices

C341S153000

Reexamination Certificate

active

06844835

ABSTRACT:
A digital-analog converter (DAC) cell circuit. The circuit includes a current source, a first resistor, a second resistor, a first MOSFET, a second MOSFET, a third MOSFET and a forth MOSFET. The first MOSFET has a source and a drain connected to the current source and the first resistor, respectively, and a gate receiving a first control signal. The second MOSFET has a source and a drain connected to the current source and the second resistor, respectively, and a gate receiving a second control signal. The third MOSFET has a source and a drain connected to the source and drain of the first MOSFET, respectively, and a gate receiving a third control signal. The fourth MOSFET has a source and a drain connected to the source and drain of the second MOSFET, respectively, and a gate receiving a fourth control signal. The third control signal is a signal delayed of the first signal and the forth control signal is a signal delayed of the second signal. The delayed control signal can be used to control the slew rate of current DAC cell, thus reduce the package inductance induced L di/dt noise. Also it can be used to reduce the voltage fluctuations during current switching so as to get fast settling current.

REFERENCES:
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patent: 5838271 (1998-11-01), Park
patent: 6031366 (2000-02-01), Mitsuishi
patent: 6160507 (2000-12-01), Carbou et al.

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