DAC architecture for an ADC pipeline

Details DAC architecture for an ADC pipeline DAC architecture for an ADC pipeline

2007-12-11

2009-08-25

Jeanglaude, Jean B (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C341S155000, C341S161000

Reexamination Certificate

active

07579975

ABSTRACT:
A residue block in a stage of a pipeline ADC processing differential signals contains multiple pairs of capacitors. During a hold phase of operation, one capacitor of a pair is connected to a positive reference voltage, and the other capacitor is connected to a negative reference voltage if the input signal exceeds a corresponding threshold voltage. When the input signal does not exceed the corresponding threshold voltage, both capacitors of the pair are connected either to the positive or the negative reference voltage. As a result, the need for a common mode reference voltage may be eliminated, and the residue block can be implemented with a smaller area.

REFERENCES:
patent: 6097326 (2000-08-01), Opris et al.
patent: 6909391 (2005-06-01), Rossi
patent: 2006/0279448 (2006-12-01), Lu
patent: 2007/0290915 (2007-12-01), Morimoto

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