DA converter

Details DA converter DA converter

2001-08-29

2003-05-27

JeanPierre, Peguy (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Digital to analog conversion

C341S155000

Reexamination Certificate

active

06570520

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. 2000-259232, filed on Aug. 29, 2000; the entire contents of which are incorporated herein by reference.
FIELD OF THE INVENTION
This invention relates to a DA converter, and more particularly, to a circuit for dividing a voltage depending on resistance components of a device and converting an input digital data to an analog value.
BACKGROUND OF THE INVENTION
Various types of DA converter for converting digital data to analog values are known. Among them, those of the resistor string type and the R-2-R type using resistors are widely used as incorporated types in integrated circuits. They each have a configuration combining a plurality of resistors and a MOS transistor connected in series thereto such that the resistors are switched by switching elements controlled by a digital data, thereby to obtain a desire analog value.
In the configuration mentioned above, accuracy of resistors and characteristics of MOS transistors, such as ON resistance, large affect the accuracy of the analog output value. These parameters, however, vary independently from each other due to manufacturing fluctuation of integrated circuits. In general, therefore, they do not always exhibit designed values.
FIG. 4
is a circuit diagram that shows one of conventional DA converters, which has a resistor string type configuration connecting N resistors R
1
through RN and a MOS transistor that are connected in series.
In the configuration of
FIG. 4
, resistors R
1
-RN have the function of dividing a voltage between a high potential reference voltage VrefH and a low potential reference voltage VrefL and generating analog voltages V
1
through VN whereas the MOS transistor M
1
plays the role of a switch that prevents a flow of a current from the high potential reference voltage VrefH to the low potential reference voltage VrefL and useless consumption of the power thereby while the DA converter is in rest. That is, when the DA converter is in rest, a power-down signal PDB maintains the drain current of the MOS transistor M
1
substantially zero to prevent consumption of the current.
A digital input
12
is converted by a decoder
11
to a selection signal corresponding to the digital data, and one of switches SW
1
through SWN associated with analog voltages V
1
-VN is selected. As a result, one of analog voltages V
1
-VN is selected and output as the analog output
13
. Switches SW
1
-SWN can be realized by using MOS transistors.
Let all of resistance values of respective resistors R
1
-RN be Rr and let the ON resistance of the MOS transistor M
1
be Ron. Then, the full scale voltage of the DA converter is
(VrefH-VrefL)×Rf×N/(Rr×N+Ron)  (1)
In order to ensure that the full scale voltage is constant without manufacturing fluctuation among integrated circuits, it is necessary to design the ON resistance Ron to be sufficiently smaller than resistance Rr×N. To design the ON resistance Ron to be small, ratio of the channel width of the MOS transistor is required to be large relative to the channel length. This directly invites an increase of the chip area.
On the other hand, to ensure a high operating frequency of the DA converter, the time constant of the circuit itself has to be small. In this case, the resistance value of the resistors R
1
-RN must be small. For this purpose, ON resistance Ron of the MOS transistor M
1
is required to be additionally smaller, which is an additional factor leading to a further increase of the chip area.
FIG. 5
is a circuit diagram that shows another conventional DA converter configured to divide a digital input signal to higher-order bits and lower-order bits and combine two DA converter blocks, one for higher-order bits and the other for lower-order bits.
In the configuration of
FIG. 5
, resistors RM
1
-RMN have function of dividing a voltage between a high potential reference voltage VrefH and a low potential reference voltage VrefL and generating analog voltages V
1
-VN whereas the MOS transistor M
1
plays the role of a switch that prevents a flow of a current from the high potential reference voltage VrefH to the low potential reference voltage VrefL and thereby prevents useless consumption of the power while the DA converter is in rest. That is, when the DA converter is in rest, a power-down signal PDB maintains the drain current of the MOS transistor M
1
substantially zero to prevent consumption of the current.
Connected to low-potential terminals of the resistors RM
1
-RMN-
1
are MOS transistors MA
1
-MAN-
1
that are selectively turned ON by selection signals Vg-VgN-
1
, and drain output is a secondary high potential reference voltage VH.
On the other hand, connected to low-potential terminals of the resistors M
2
-RMN are MOS transistors MB
1
-MBN-
1
that are selectively turned ON by selection signals Vg
1
-VgN-
1
, and the drain output is a secondary low potential reference voltage VL.
A digital input
23
of the block of higher-order bits is converted to a selection signal Vg
1
-VgN-
1
corresponding to the digital data by a decoder
21
, and it is given to a MOS transistor MA
1
-MAN-
1
and a MOS transistor MB
1
-MBN-
1
. As a result, a corresponding MOS transistor is turned ON. This results in the high-potential voltage of one of resistors RM
2
-RMN being selected and output as the secondary high potential reference voltage VH and the low-potential voltage of same being selected and output as the secondary low potential reference voltage VL.
The resistors RL
1
through RLM have the function of dividing a voltage between the secondary high potential reference voltage VH and the secondary low potential reference voltage VL and generating analog voltages VL
1
-VLM.
A digital input
24
to the block of lower-order bits is converted to a selection signal corresponding to the digital data by a decoder
22
, and one of switches SW
1
-SWM associated with respective analog voltages VL
1
-VLM is selected. As a result, one of analog voltages VL
1
-VLM is selected and output as the analog voltage value output
25
. Switches SW
1
-SWM can be realized by using MOS transistors.
In summary, the DA converter having the configuration of
FIG. 5
selects a voltage range which is data of a higher-order bit, and selects and outputs to the analog output
25
one of analog voltage values obtained by further dividing the selected voltage range with data of a lower-order bit.
For improving the accuracy of this circuit, it is necessary to maintain the ON resistance of MOS transistors MA
1
-MAN-
1
and MOS transistors MB
1
-MBN-
1
sufficiently smaller than the total of resistance values of resistors RL
1
-RLM of lower-order bits. For this purpose, the ratio of the channel width relative to the channel length must be large, that is, the channel width must be wider, and this inevitably increases the area occupied on an integrated circuit.
FIG. 6
is a circuit diagram that shows a still further conventional DA converter having a R-w-R type configuration.
As apparent from
FIG. 6
as well, this DA converter is made up of resistors RC
1
-RCN-
1
, RD
0
-RDN and MOS transistors MD
1
-MDN and MD
1
B-MDNB.
MOS transistors MD
1
-MDN are each controlled by a signal VgD
1
-VgDN corresponding to digital inputs
31
. On the other hand, MOS transistors MD
1
B-MDNB are controlled by signals VgD
1
B-VgDNB which are inversion signals of signals VgD
1
-VgDN. That is, they are so controlled that, while one is ON, the other is OFF, or while one is OFF, the other is ON, in each of associated pairs of MOS transistors MD
1
-MDN and MOS transistors MD
1
B-MDNB.
MOS transistors MD
1
-MDNB are connected to the high potential reference voltage VrefH whereas MOS transistors MD
1
B-MDNB are connected to the low potential reference voltage VrefL. Depending on a ON-OFF combination corresponding to the digital inputs
31
, the high potential reference voltage VrefH or the low potential reference voltage VrefL is supplied to a

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