Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Particular stable state circuit
Reexamination Certificate
1999-11-05
2001-11-27
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Particular stable state circuit
C327S202000, C327S225000
Reexamination Certificate
active
06323710
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention concerns a D-type master-slave flip-flop, advantageously one implemented in the CMOS technology.
2. Description of the Prior Art
A master-slave flip-flop of the above kind is described in “Analyse et synthèse des systèmes logiques” [“Analysis and synthesis of logic systems”], by D. Mange, Vol. V of “Traité d'électricité” [“Treatise on electricity”], Ecole Polytechnique Fédérale de Lausanne, Switzerland, published by Editions Georgi, 1978, page 260.
As shown in
FIG. 1
on the accompanying drawings, the prior art master-slave flip-flop includes a master unit MA receiving an input variable D and producing two first intermediate variables M and NM, both of which are a function of the input variable. The master-slave flip-flop also includes a slave unit E adapted to form at least one output variable Q and/or NQ of the flip-flop from said first intermediate variables M and NM. A transfer unit T connected between the master unit MA and the slave unit E respectively includes, for each of said output variables Q and NQ, at least one logic gate P
1
and P
2
adapted to combine the first intermediate variables N and NM applied to it with a clock signal CK, producing two second intermediate variables X and Y which are applied to the slave unit E.
In the prior art embodiment shown, the master unit MA comprises two NAND gates P
3
and P
4
and the slave unit E comprises two NAND gates P
5
and P
6
.
The essential advantages of this type of prior art flip-flop are that they have no race (critical travel) and do not need a clock inverter. Also, the clock signal is applied only to gates P
1
and P
2
of the transfer unit T. See document EP 0 734 122 for a detailed explanation of the “race” concept (which is well known in the art).
However, these flip-flops have a drawback due to their sensitivity to the slope of the rising or falling edge of the pulses of the clock signal CK.
FIGS. 2 and 3
of the appended drawings show the consequences of this sensitivity of the flip-flop to the slope of the clock signal.
FIG. 2
shows that, if the clock signal CK changes state, for example from “1” to “0”, the variable X goes from “0” to “1” and the variable M goes from “1” to “0”. Considering the variable Y during this same process, it can be seen that the rise in the variable X creates an uncertainty or glitch in the variable Y if the clock signal is relatively slow to reach its low level.
FIG. 3
shows this phenomenon by means of a model of the transfer unit T whose gate P
2
receives the clock signal CK subject to a time-delay Dl of duration &dgr;w and whose gate P
1
supplies the variable X subject to a time-delay D
2
of duration &dgr;x. There is a glitch in the variable Y if &dgr;w>&dgr;x, which can result from an erroneous change of state of the slave unit E in response to a 1→0→1 glitch in the variable Y.
The object of the invention is to provide a D-type master-slave flip-flop in which the influence of the slope of the flanks of the clock signal pulse is greatly reduced, if not completely eliminated.
SUMMARY OF THE INVENTION
The invention therefore consists in a CMOS D-type master-slave flip-flop including:
a master unit receiving an input variable and producing two first intermediate variables as a function of the input variable,
a transfer unit connected to the master unit and including at least two logic gates and a clock connection adapted to receive a clock signal and which is connected to one input of each of the gates, which are adapted to supply respective second intermediate variables as a function of the input variable and the clock signal and are looped to the master unit, and
a slave unit connected to the transfer unit to form at least one output variable of the flip-flop from the second intermediate variables, wherein:
another input of a first gate of the transfer unit is connected to the master unit to receive directly the true value of one of the variables supplied by the master unit,
another input of the second gate of the transfer unit is connected to the master unit to receive therefrom the complement of the same first intermediate variable, and
the second intermediate variables are independent of each other.
With a D-type flip-flop having the above features there is a very low risk of generating unstable situations corresponding to glitches. The flip-flop can be implemented using a small number of transistors, without compromising the switching time, and can use a branch topography in which each branch includes only one P-type transistor and at most two N-type transistors in series.
According to other advantageous features of the invention:
the master unit comprises an inverter to provide the complement of the same first intermediate variable;
the master, transfer and slave units each comprise two NAND gates or two NOR gates;
a first gate of the master unit is adapted to receive at a first input the input variable and at a second input one of the looped intermediate variables, a second gate of the master unit is adapted to receive at a first input the output of the first gate and at a second input the other of the looped second variables, and the output of the second gate is connected to an input of the first and second gates of the transfer unit, respectively directly and via the inverter;
the master unit comprises an AND gate receiving at its inputs the input variable and one of the looped second intermediate variables and a NOR gate having one input connected to the output of the AND gate and adapted to receive at another input the other looped intermediate second variable, the output of the NOR gate being connected to the transfer unit and to the inverter;
the slave unit includes two logic gates each having a first input connected to receive a respective one of the second intermediate variables and a second input connected to the output of the other logic gate of the slave unit, the outputs of the logic gates each delivering one of the output variables;
the slave unit comprises an AND gate, one input of which is adapted to receive one of the second intermediate variables and whose output is connected to a first input of a NOR gate whose other input is adapted to receive, in inverted form, the other of the second intermediate variables, the other input of the AND gate is connected to the output of an inverter supplying a first of the output variables, and the output of the NOR gate is connected to the inverter and supplies the other of the output variables;
the transfer unit has an additional control input on at least one of its gates to confer a set or reset function on the flip-flop.
The invention also consists in the use of a D-type master-slave flip-flop as defined above as a divider by
2
, wherein one of the output variables is looped to constitute the input variable and the second output variables constitute outputs in antiphase at a frequency which is half the frequency of the clock signal.
Other features and advantages of the invention will become apparent in the course of the following description, which is given by way of example only and with reference to the accompanying drawings.
REFERENCES:
patent: 3588546 (1971-06-01), Lagamann
patent: 3622803 (1971-11-01), Cooper
patent: 4506165 (1985-03-01), Gulati
patent: 4797575 (1989-01-01), Lofgren
patent: 5781053 (1998-06-01), Ramirez
patent: 5786719 (1998-06-01), Furutani
Arm Claude
Masgonty Jean-Marc
Piguet Christian
CSEM Centre Suisse d'Electronique et de Microtechnique SA
Cunningham Terry D.
Tra Quan
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