D-type flipflop

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Particular stable state circuit

Reexamination Certificate

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Details

C327S202000, C327S217000

Reexamination Certificate

active

07109772

ABSTRACT:
A flipflop having a clock input for applying a clock signal, a data input for applying a data signal, a noninverting output and an inverting output, where the flipflop has a first holding element with a first feedback loop and a second holding element with a second feedback loop, where the first and second feedback loops each have a first node and a second node, where the first holding element is designed such that upon a first clock edge of the clock signal the logic value of the data signal is transferred to the first holding element and the logic value of the data signal is made available on the first node in the first feedback loop, where the first node in the first feedback loop is coupled to the first node in the second feedback loop in order to transfer the signal value which is on the first node in the first feedback loop to the second holding element upon a second clock edge of the clock signal and to output the signal value on the noninverting output, wherein the second node in the first feedback loop is coupled to the second node in the second feedback loop in order to transfer the inverted signal value which is on the second node in the first feedback loop to the second holding element upon the second clock edge of the clock signal, where the second node in the second feedback loop corresponds to the noninverting output and the first node in the second feedback loop corresponds to the inverting output.

REFERENCES:
patent: 4939384 (1990-07-01), Shikata et al.
patent: 5173870 (1992-12-01), Sukashita et al.
patent: 5189315 (1993-02-01), Akata
patent: 5281865 (1994-01-01), Yamashita et al.
patent: 2002/0005745 (2002-01-01), Robertson et al.
patent: 2003/0030474 (2003-02-01), McGowan
patent: 2 202 866 (1988-10-01), None
patent: 62-9791 (1987-01-01), None
patent: 62-40816 (1987-02-01), None
patent: 63103511 (1988-05-01), None
patent: 2-210907 (1990-08-01), None
Weste et al. (Principles of CMOS VLSI Design: A Systems Perspective, 1993, Addison Wesley, 2nd Edition, p. 91.

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