D.T.R.M. data timing recovery module

Details D.T.R.M. data timing recovery module D.T.R.M. data timing recovery module

1999-07-23

2001-07-03

Le, Amanda T. (Department: 2634)

Pulse or digital communications

Synchronizers

Self-synchronizing signal

C375S376000, C327S159000, C331S025000

Reexamination Certificate

active

06256361

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
The present invention relates to a data timing recovery module for clock recovery, more particular to clock extraction.
DESCRIPTION OF RELATED ART
Clock recovery is a well known method to recover timing on a signalling link. The simplest way to send data on a serial electrical link is to use two different physical connections, one for data and one for timing, clock. One of the connections can be avoided by extracting the timing information from the data by means of a special code, for example CMI, HDB3, AMI etc. By using one of these transmission codes, the normal data bandwidth will be differently distributed and some high frequency components will be generated. These components are used to extract the timing information. This procedure is called “clock recovery.”
By using one of the previous codes the data bandwidth will be enlarged. Because of that, it will be necessary to increase the transmission media performance, and consequently more expensive. This problem has been solved by using codes that preserve the bandwidth characteristics, but the timing recovery operation is more difficult. Circuits normally used for the clock extraction need one or more data transitions every few bit group, or the clock could not be extracted. The code used must guarantee this condition, e.g. non-return to zero (NRZ) scrambled data. The clock extraction problem is easily solved, especially if the data pattern used is poor of transitions.
There are two existing methods to realize the clock extraction from an NRZ scrambled data link: The first method consists of a narrow band phase locked loop (PLL), circuit with a digital phase comparator that continuously measures the phase difference between the positive (or negative) data transition and the clock edges which are generated by a local oscillator. The frequency of this oscillator will be adjusted so as to eliminate the phase difference between data transitions and clock edges. This is an expensive solution because often it is difficult to implement by standard discrete components. Furthermore, the flexibility is limited using this method because all the physical parameters such as frequency, pattern, etc. cannot be changed to cover other possible requirements.
The second method to extract the timing information consists of the application of a Q tank followed by a high gain selective amplifier stage. The Q tank is realized by a simple LC circuit, or by using a SAW resonator, continuously stimulated from data edges transitions. If a LC resonator is used, a special inductor is needed in order to have a sufficiently large Q value to preserve the timing information during long “0” or “1” sequences. This is a more flexible solution, but it has lower performance than the one described previously. The recovered clock, for example, is affected by jitter because the S/N ratio is very low at the Q tank output, especially if the pattern used is poor of transitions.
JP 88-174442 by Masushita et al, have an oscillator in free running mode to guarantee a timing clock at the output XXX. The invention is to suppress the appearance of noise and jitter in periodical reproduction output, by obtaining a required iming clock based on self-advancing oscillation.
SUMMARY
One problem this invention solves is to extract a clock signal at high rate.
Another problem this invention solves is to preserve the timing information during long “0” or “1” sequences.
This invention solves the clock recovery problem in a new way by using a known effect which was originally used for another purpose. The purpose was for frequency modulation receivers, carrier modulation systems and to multiply or divide a clock frequency by an integer number.
The present invention is a data timing recovery system, i.e. a data timing recovery module (DTRM), which is based on an injection locked oscillator, ILO. This invention extracts the timing information from a high bit rate data signal, e.g. scrambled NRZ coming from optical or electrical interfaces. Other data patterns than NRZ can be used. The timing recovery system uses a lock-in phenomena in the ILO. The timing information will be extracted even if the data stream is composed by long sequences of bit logic level “1” or by long sequences of bit logic level “0” repeatedly. At every data transition event, a zero crossing circuit generates a pulse which is used to phase lock the frequency generated by the oscillator.
This invention has at least two parts; the pulse generator circuit, and the injection locked oscillator. Other parts that can be used are a clock extractor circuit including the ILO, a phase aligner circuit and a clock killer circuit.
One advantage is that the DTRM can extract time information from high Mbit/s signals at a low cost.
Another advantage is that the DTRM can extract time information from high Mbit/s signals at high performance.
Another advantage is that the DTRM can be made to be very small in its dimensions.
Yet another advantage is that the DTRM is easy adaptable to different bit rate operation.
The invention is now being described further with the help of the detailed description of preferred embodiments and attached drawings.


REFERENCES:
patent: 4918406 (1990-04-01), Baumbach et al.
patent: 5050167 (1991-09-01), Izadpanah
patent: 5276712 (1994-01-01), Pearson
patent: 5574756 (1996-11-01), Jeong
patent: 5761255 (1998-06-01), Shi
patent: 5812619 (1998-09-01), Runaldue
patent: 5987085 (1999-11-01), Anderson
patent: 6133802 (2000-10-01), Ma
patent: 63-174442 (1988-07-01), None
patent: 7-143200 (1995-06-01), None

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