D-Latch circuit using CMOS transistors

Details D-Latch circuit using CMOS transistors D-Latch circuit using CMOS transistors

1984-01-23

1986-02-04

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307288, 307272A, 307452, 307585, 377117, 377121, 377127, H03K 19003, H03K 19096, H03K 3356, G11C 1140

Patent

active

045688427

ABSTRACT:
A latch circuit includes a CMOS inverter to which a logic signal is applied to the input through an input terminal, which inverter continues to supply an output signal to its output terminal; and first depletion type p and n-channel MOS transistors connected in series to each other, with the CMOS inverter being interposed therebetween. The latch circuit further includes second depletion type n and p-channel MOS transistors which are supplied, at their gates, with an output signal from the CMOS inverter; the second n-channel MOS transistor being connected between the first p-channel MOS transistor and a power supply terminal, and the second p-channel MOS transistor being connected between the first n-channel MOS transistor and a ground.

REFERENCES:
patent: T955006 (1977-02-01), Cavaliere et al.
patent: 3720841 (1973-03-01), Suzuki
patent: 3937982 (1976-02-01), Nakajima
patent: 4122360 (1978-10-01), Kawagai et al.
patent: 4255723 (1981-03-01), Ebihara
patent: 4472643 (1984-09-01), Furuyama
patent: 4521695 (1985-06-01), Mazin et al.
patent: 4532439 (1985-07-01), Koike
Elmasry et al., "A DOL CMOS Static Memory Cell," IEEE Journal of Solid-State Circuits, vol. SC-16, No. 5, Oct. 1981.

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