D.C. Voltage bias circuit in an integrated circuit

Details D.C. Voltage bias circuit in an integrated circuit D.C. Voltage bias circuit in an integrated circuit

1984-04-11

1984-12-18

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307304, 330296, 330302, 357 23, H03K 1716, H03F 152

Patent

active

044892454

ABSTRACT:
In an integrated circuit having an amplifier with its input terminal connected to a signal input terminal, a D.C. voltage bias circuit is provided which includes a D.C. bias voltage generator and a depletion mode MOS transistor connected at its source-drain path between the bias voltage generator and the signal input terminal and coupled at its gate electrode to either its source or its drain thus preventing breakdown of the gate insulating film of the depletion mode MOS transistor resulting from a surge voltage from the signal terminal.

REFERENCES:
patent: 3417464 (1968-12-01), Fang et al.
patent: 3775693 (1971-11-01), Proebsting
patent: 3819952 (1974-06-01), Enomoto et al.
patent: 3913026 (1975-10-01), Koehler
patent: 3942047 (1976-03-01), Buchanan
patent: 4161664 (1979-07-01), Kawagoe et al.
patent: 4282556 (1981-08-01), Ipri
patent: 4288829 (1981-09-01), Tango
patent: 4438449 (1984-03-01), Usuda
Mead and Conway, Introduction to VLSI Systems, Addison-Wesley Pub. Co., Mass., Oct. 1980, pp. 33-37.

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