D.C. Stable semiconductor memory cell

Details D.C. Stable semiconductor memory cell D.C. Stable semiconductor memory cell

1974-12-23

1976-04-06

Hecker, Stuart N.

Communications: electrical

Digital comparator systems

307291, 340173R, G11C 700, G11C 800, G11C 1140

Patent

active

039493857

ABSTRACT:
Disclosed is a field effect transistor (FET) memory array in which each of the cells forming the array comprises four FET's. The first and second of the four FET devices are cross-coupled while the third and fourth FET devices form loads for the cross-coupled pair. D.C. stability is achieved by conditioning the load FET devices into partial conduction during the stand-by state of the memory cell.

REFERENCES:
patent: 3540007 (1970-11-01), Hodges
patent: 3550097 (1970-12-01), Reed
Baitinger et al., MOSFET Storage Cell, IBM Technical Disclosure Bulletin, Vol. 13, No. 10, 3/71, p. 3160, S1509 0037.
Pleshko, Field-Effect Memory Cell with Low Standby Power and High Switching Speed, IBM Technical Disclosure Bulletin, Vol. 8, NO. 12, 5/66, pp. 1838-1839.

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