D. C. Stable semiconductor memory cell

Details D. C. Stable semiconductor memory cell D. C. Stable semiconductor memory cell

1974-12-23

1976-04-06

Canney, Vincent P.

Communications: electrical

Digital comparator systems

G11C 702, G11C 1124

Patent

active

039493830

ABSTRACT:
Disclosed is a field effect transistor (FET) memory array in which each of the cells forming the array comprises four FET's. The first and second of the four FET devices are cross-coupled while the third and fourth FET devices form loads for the cross coupled pair. D.C. stability is achieved by conditioning the load FET devices into partial conduction during the stand-by state of the memory cell.

REFERENCES:
patent: 3157859 (1964-11-01), Moore et al.
patent: 3161858 (1964-12-01), Sanders et al.
patent: 3535699 (1970-10-01), Gaensslen et al.
patent: 3576571 (1971-04-01), Booher
patent: 3806898 (1974-04-01), Askin
patent: 3836894 (1974-09-01), Cricchi
patent: 3868656 (1975-02-01), Stein et al.

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