D.C. controlled attenuator

Details D.C. controlled attenuator D.C. controlled attenuator

1976-10-07

1977-12-06

Richardson, Robert L.

Facsimile and static presentation processing

Static presentation processing

Attribute control

307251, 307255, 307264, 307313, 323 23, 330284, 358 40, H04N 9537, H03F 318, H03G 310

Patent

active

040620425

ABSTRACT:
A D.C. controlled attenuator which is particularly useful as a D.C. controlled video attenuation circuit providing three tracking channels that can be used as a tracking contrast control in an RGB monitor includes an integrated circuit having at least six MOS field effect transistors on a common substrate, the transistors being of N-channel and P-channel type and being arranged in the three groups of two each connected in complementary symmetry. In each group the gate electrodes of the N-channel and P-channel transistors are connected together, their drain electrodes are connected together and a source of D.C. potential is connected between their source electrodes in parallel. A variable resistor is connected between the gate electrodes of the transistors of a group and the drain electrodes of those transistors providing a feed forward signal path that also preferably includes a variable inductance coil. Input signals are supplied to the gate electrodes of the transistors, and the magnitude of the D.C. potential of the source of D.C. potential can be varied. By adjusting the value of the resistor in the feed forward signal path, cancellation of the signal at the drain junction of the COS MOS amplifier can be achieved at maximum gain of the amplifier, so that when the gain of the amplifier is reduced, less attenuation results.

REFERENCES:
patent: 3914702 (1975-10-01), Gehweiler
patent: 3919712 (1975-11-01), Izumisawa et al.

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