D/A for controlling an oscillator in a phase locked loop

Details D/A for controlling an oscillator in a phase locked loop D/A for controlling an oscillator in a phase locked loop

1996-06-04

1998-04-21

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

327157, 327159, 348505, 348512, 331 1A, H03L 706

Patent

active

057421919

DESCRIPTION:

BRIEF SUMMARY
This invention relates to Phase Locked Loops (PLL's), and more particularly to apparatus for generating a phase/frequency control signal of a controllable oscillator in the feedback loop.
Phase Locked Loops are circuits well known in the communications arts, for synchronizing a variable local oscillator with the phase and/or frequency of a component of a transmitted signal. Typically such circuitry includes a phase detector which is responsive to the transmitted signal and the output of the local oscillator, to generate a phase error signal proportional to the difference between a component of the transmitted signal and the oscillator output. The phase error signal is coupled to control the oscillator rate of the variable oscillator.
U.S. Pat. No. 5,159,292 in the names of Canfield, et al., entitled, ADAPTIVE PHASE LOCKED LOOP describes a PLL for synchronizing a voltage controlled oscillator (VCO) to a subcarrier burst component in each active horizontal line of a composite video signal. A phase error signal digitally represented as a parallel phase error data word is applied via a digital-to-analog (D/A) converter to produce an analog signal having a magnitude that is determined by the value of the phase error data word. The analog signal that undergoes signal integration process is applied to control the phase/frequency of the VCO.
In one prior art, such D/A converter is realized using a pulse-width-modulator (PWM). During each horizontal line, the PWM generates a single pulse, when phase correction is required, having a pulse width that is modulated in accordance with the value of the phase error data word. The modulated pulse is applied to a charge pump arrangement. The charge pump arrangement charges/discharges an integrating capacitor, during the pulse. The change in the capacitor voltage is determined by the pulse width or the value of the phase error word. The capacitor voltage controls the VCO frequency. Disadvantageously, because only a single pulse occurs during each horizontal line, the size of the integrating capacitor may be relatively large.
For reducing the size of the integrating capacitor, a bit rate multiplier, embodying an inventive feature, is utilized as the D/A converter. The bit rate multiplier produces pulses at a higher frequency than the horizontal frequency. The bit rate multiplier includes a memory. The memory retains phase information of the pulses from each horizontal line to the immediately following one. Such an arrangement prevents errors in the analog output signal.
A phase locked loop circuit, embodying an aspect of the invention, generates an oscillatory signal phase locked to a synchronizing component signal of an input signal. A controllable oscillator generates the oscillatory signal. A phase error signal that is indicative of a phase error of the oscillatory signal is generated. A first control signal having pulses of equal pulse width and a frequency that varies in accordance with a magnitude of the phase error signal are generated. A filter responsive to the first control signal generates a filtered control signal that is coupled to the oscillator for varying a phase of the oscillatory signal.
FIG. 1 illustrates a phase-lock-loop circuit including a digital-to-analog converter, embodying an aspect of the invention;
FIGS. 2a-2d illustrate waveforms useful for explaining the operation of the converter of FIG. 1; and
FIG. 3 illustrates a second embodiment of the converter of FIG. 1.
Referring to FIG. 1, an analog video signal from, for example, a television tuner, not shown, is applied to an analog-to-digital converter (ADC) 30. A digitized version of the analog signal is coupled from the output of the ADC to a horizontal synchronizing signal separator 31 and a phase detector 32. Separator 31 produces horizontal synchronizing pulses, which are coupled to phase detector 32, to condition the phase detector to operate in a phase measuring mode during chrominance reference burst intervals. Phase detector 32 is responsive to the digitized video signal compared in phase de

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patent: 5159292 (1992-10-01), Canfield et al.
patent: 5373255 (1994-12-01), Bray et al.
patent: 5459766 (1995-10-01), Huizer et al.

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