Coded data generation or conversion – Analog to or from digital conversion – Digital to analog conversion
Patent
1987-01-09
1989-07-25
Roskoski, Bernard
Coded data generation or conversion
Analog to or from digital conversion
Digital to analog conversion
341144, H03K 1302
Patent
active
048518441
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD
This invention relates generally to a D/A converter which converts a digital signal into an analog signal (hereinafter be simply referred to as "the D/A conversion"), and more particularly to an integrating type D/A conveter which is preferably adapted to convert a plurality of digital signals into an analog output signal.
BACKGROUND ART
There has been conventionally proposed an example of a D/A conveter which effects the D/A conversion of a product of a plurality of digital input signals, e.g. as shown in FIG. 1. Referring to FIG. 1, reference numeral 1 designates an input terminal to which a digital signal is supplied and this input terminal 1 has n terminals 1.sub.0, 1.sub.1, 1.sub.2, . . . , 1.sub.n corresponding to the number of bits of a digital signal to be inputted thereto The digital signal having n bits is parallelly inputted such that the most significant bit (MSB) thereof is supplied to the terminal 1.sub.0, the bit next to the MSB to the terminal 1.sub.1, respective bits are supplied sequentially to the respective terminals in the same manner, and finally the least significant bit (LSB) thereof is supplied to the terminal 1.sub.n.
The n-bit digital signals simultaneously inputted to the terminals 1.sub.0 -1.sub.n are supplied to a data register 2 through input terminal groups 3 and 4 in predetermined conditions. To be specific, the input terminal groups 3 and 4 respectively have m and (m-n-1) input terminals 3.sub.0 -3.sub.m and 4.sub.0 -4.sub.m. The terminal 1.sub.0 is connected only to the terminal 3.sub.0, and the terminal 1.sub.n only to the terminal 4.sub.m. Further, the terminal 1.sub.1 is connected to input terminals 3.sub.1 and 4.sub.0, the terminal 1.sub.2 to terminals 3.sub.1 and 4.sub.1, and in the same manner, respective terminals of the input terminal group 1 are connected to respective input terminals of the input terminal groups 3 and 4.
Therefore, the input terminal 3.sub.0 the data register 2 is supplied with the most significant bit of the input digital signal, the input terminal 3.sub.1 bit next to the most significant bit of the same input digital signal, and in the same manner as above, the respective input terminals 3.sub.2, 3.sub.3, . . . , 3.sub.m are supplied with the respective bits of the digital input signal. Further, the input terminal 4.sub.0 of the data register 2 is supplied with the second most significant bit of the input digital signal, the input terminal 4.sub.1 with the third significant bit of the same, and in the same manner, respective input terminals 4.sub.2, 4.sub.3, . . . , 4.sub.m are sequentially supplied with the respective bits of the digital input signal. At the last, the input terminal 4m is supplied with the least significant bit of the input digital signal supplied to the terminal 1m.
The data register 2 switches the digital signals inputted to the input terminal groups 3 and 4 and delivers the same to an output terminal group 5 which has m output terminals 5.sub.0, 5.sub.1, . . . , 5.sub.m. The digital signal outputted to the output terminal group 5, i.e. the signal inputted to the input terminal group 3 or that inputted to the input terminal group 4, is selected by a change-over control signal supplied from a control circuit 7 to the data register 2 through its control terminal 6.
Therefore, delivered to the output terminal group 5 is, in response to the switching operation by the data register 2, either the digital signal from the input terminal group 3, that is, the digital signal comprising from the most significant bit to the second least significant bit or the digital signal from the input terminal group 4, that is, the digital signal comprising from the second most significant bit to the least significant bit.
The manner which of the digital signals supplied to the input terminal groups 3 and 4 is delivered to the output terminal 5 of the data register 2 by switching the same is based upon the result of a determination made as to whether or not the information area of the inputted digital signal exceeds a predetermi
REFERENCES:
patent: 3422423 (1969-01-01), Kaszynski et al.
The Engineering Staff of Analog Devices, Inc., Analog-Digital Conversion Handbook, 6/1972, pp. I-61 to I-64.
Roskoski Bernard
Sony Corporation
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