D/A converter with high jitter resistance

Details D/A converter with high jitter resistance D/A converter with high jitter resistance

2003-04-08

2004-05-11

Tokar, Michael (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Digital to analog conversion

C341S143000, C341S165000, C341S172000

Reexamination Certificate

active

06734816

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a D/A converter mounted on audio equipment for converting an audio signal (1-bit digital signal) to an analog signal.
2. Description of Related Art
FIG. 24
is a block diagram showing a configuration of a part of audio equipment to which a conventional D/A converter is applied. In
FIG. 24
, the reference numeral
1
designates a delta-sigma modulator (called “&Dgr;&Sgr;-modulator” from now on) for carrying out parallel-to-serial conversion of a 16-bit parallel audio signal, for example, in synchronization with a clock signal CLK, and for outputting a 1-bit serial audio signal (called “l-bit signal” from now on);
2
designates a 1-bit D/A converter for converting the 1-bit signal output from the &Dgr;&Sgr;-modulator
1
to an analog signal in synchronization with a clock signal clk with a frequency lower than that of the clock signal CLK supplied to the &Dgr;&Sgr;-modulator
1
; and
3
designates a filter circuit for eliminating noise components contained in the output signal of the 1-bit D/A converter
2
, thereby outputting a signal component.
Next, the operation of the conventional equipment will be described.
Receiving the 16-bit parallel audio signal, the &Dgr;&Sgr;-modulator
1
carries out the parallel-to-serial conversion of the audio signal in synchronization with clock signal CLK, and outputs a 1-bit signal, that is, a 1-bit serial audio signal.
FIG. 25A
illustrates frequency characteristics of the 1-bit signal, in which fs designates the frequency of the clock signal CLK. The 1-bit signal includes large noise components besides the signal component.
Receiving the 1-bit signal from the &Dgr;&Sgr;-modulator
1
, the 1-bit D/A converter
2
carries out the digital-to-analog conversion of the 1-bit signal.
More specifically, as shown in FIG.
26
(
a
), when the 1-bit signal output from the &Dgr;&Sgr;-modulator
1
is at a high level, the 1-bit D/A converter
2
generates a first reference potential, whereas when the 1-bit signal is at a low level, it generates a second reference potential lower than the first reference potential.
In this case, the ideal waveform of the output signal of the 1-bit D/A converter
2
is as shown in FIG.
26
(
a
). In practice, however, there arise overshoots and undershoots as shown in FIG.
26
(
b
) at transitions of the voltage waveform. Accordingly, area components (energy S) per cycle of the output signal fluctuate, which presents a problem of being unable to maintain the linearity of the output signal corresponding to the 1-bit signal.
In view of this, the conventional 1-bit D/A converter
2
employs an RTZ (Return-To-Zero) scheme that forcedly drops the latter half of the one cycle to the second reference potential as shown in FIG.
26
(
c
).
The RTZ scheme, however, sometimes presents a problem in that since it increases the number of transitions (edges) of the output signal, the area components of the output signal can fluctuate because of jitter at the edges as illustrated in
FIG. 27
, thereby bringing about noise.
FIG. 25B
shows the frequency characteristics of the output signal of the 1-bit D/A converter
2
. It shows that although the noise components near the is reduce as compared with the frequency characteristics of the 1-bit signal, large noise components still remain.
The filter circuit
3
removes the noise components from the output signal to separate only the signal component from the output signal of the 1-bit D/A converter
2
.
With the foregoing configuration, the conventional D/A converter has a problem of degrading the SNR because the jitter due to an increase in the number of the transitions of the output signal causes additional noise. Furthermore, although it can reduce the noise component near the is, the remaining noise components present a problem of complicating the circuit configuration of the filter circuit
3
.
SUMMARY OF THE INVENTION
The present invention is implemented to solve the foregoing problems. It is therefore an object of the present invention to provide a D/A converter capable of improving the jitter tolerance and simplifying the circuit configuration of the filter circuit.
According to a first aspect of the present invention, there is provided a D/A converter including a plurality of potential generating means each for receiving a 1-bit signal from one of an input terminal and delay circuit, and a clock signal or inverted clock signal from input means or inverter for inverting the clock signal. When the clock signal or inverted clock signal is at a first signal level, they generate one of a first reference potential and a second reference potential in response to the signal level of-the 1-bit signal. When the clock signal or inverted clock signal is at a second level, they generate an intermediate potential between the first and second reference potentials. The potentials generated by the plurality of potential generating means are combined by combining means. The D/A converter can not only improve resistance to jitter, but also to simplify the configuration of a post-stage filter circuit.
According to a second aspect of the present invention, there is provided a D/A converter including a plurality of potential generating means each for receiving a level signal output from one of signal converting means and delay circuits, and for outputting a potential corresponding to the level signal. The potentials generated by the plurality of potential generating means are combined by combining means. The D/A converter can improve resistance to jitter, and to simplify the configuration of a post-stage filter circuit.


REFERENCES:
patent: 4641246 (1987-02-01), Halbert et al.
patent: 4947171 (1990-08-01), Pfeifer et al.
patent: 5272481 (1993-12-01), Sauer
patent: 5727024 (1998-03-01), Hauptmann
patent: 6031477 (2000-02-01), Mercer
patent: 6061010 (2000-05-01), Adams et al.
patent: 6628219 (2003-09-01), Dedic
David A. Johns et al., “Linearity of Two-Level converts”, Analog Integrated Circuit Design, Chapter 14, Section 14.7, pp. 560-563.

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