Coded data generation or conversion – Analog to or from digital conversion – Digital to analog conversion
Reexamination Certificate
2003-01-28
2004-08-17
Williams, Howard L. (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Digital to analog conversion
C341S154000
Reexamination Certificate
active
06778120
ABSTRACT:
This nonprovisional application claims priority under 35 U.S.C. § 119(a) on Patent Application No. 2002-019138 filed in JAPAN on Jan. 28, 2002, which is herein incorporated by reference.
FIELD OF THE INVENTION
The present invention relates to a D/A converter circuit for converting an input digital signal into an analog signal, which adopts an R-2R ladder resistor-net, and in particular to a two-stage D/A converter circuit realizing resolution enhancement by two-stage D/A conversion operation.
BACKGROUND OF THE INVENTION
A D/A (digital-analog) converter having an R-2R ladder resistor-net is a circuit for converting an input digital signal into an analog signal and outputting the converted signal. For example, the D/A converter is made up of a resistor-net
71
including a resistor having resistance value of R and a resistor having resistance value of 2R (series resistance value of R and R), a group of switches
73
connected to the resistor-net
71
and an offset level control resistor
72
, as with an R-2R ladder resister type D/A converter
70
shown in FIG.
8
.
FIG. 8
shows an example of 3-bit input, and digital input signals D
3
, D
4
and D
5
are respectively inputted to switches SW
3
, SW
4
and SW
5
making up the group of switches
73
. The digital input signal D
3
is MSB (Most Significant Bit) and the digital input signal D
5
is LSB (Least Significant Bit). An offset terminal OFFCR is provided on an end of the offset level control resistor
72
.
The following will more specifically explain operation principle of the R-2R ladder resistor type D/A converter
70
with reference to FIG.
8
. The switches SW
3
through SW
5
of the group of switches
73
control input to the resistor-net
71
according to the digital input (D
3
through D
5
) by switching the input to Vdd when the digital input is HIGH, and switching the input to Gnd when the digital input is LOW. Thus, with the input of the digital input signals D
3
through D
5
, an analog output voltage Aout can be expressed by the following equation:
Aout
={(
D
3
×2
2
+D
4
×2
1
+D
5
×2
0
)/2
3
}Vdd
+offset
Here, Dn (n=3, 4, 5) is 0 or 1 (depending on the digital input code). The offset varies depending on the voltage inputted to the offset terminal OFFCR.
As shown in FIG.
9
(
a
), when Gnd is inputted to the offset terminal OFFCR, the analog output becomes Gnd to (Vdd−1LSB), and as shown in FIG.
9
(
b
), when Vdd is inputted to the offset terminal OFFCR, the analog output becomes (Gnd+1LSB) to Vdd. Further, as shown in FIG.
9
(
c
), when the intermediate voltage value between Gnd and Vdd is inputted to the offset terminal OFFCR, the analog output becomes the intermediate value between FIG.
9
(
a
) and FIG.
9
(
b
).
The R-2R ladder resistor type D/A converter
70
outputs the analog output Aout according to the foregoing equation when the ratio of R to 2R is accurately 1:2. However, as it is clearly shown in
FIG. 8
, due to ON resistance of the switches SW
3
through SW
5
,
2
R actually becomes 2R+&agr; (&agr; is ON resistance of the switches). Therefore, in order to compensate the ratio of R side to 2R side to be 1:2, for example, Japanese Laid-Open Patent Application Tokukaisho 64-042924/1989 (published on Feb. 15, 1989), Japanese Laid-Open Patent Application Tokukaihei 02-013014/1990 (published on Jan. 17, 1990), Japanese Laid-Open Patent Application Tokukaihei 02-202227/1990 (published on Aug. 10, 1990), Japanese Laid-Open Patent Application Tokukaihei 04-138725/1992 (published on May 13, 1992) or some other publications disclose an arrangement for always turning on switches also in the R side. Note that, it is also possible to provide the resistance value of 2R side by originally subtracting by ON resistance of the switches so as to compensate the ratio of 1:2. Further, Japanese Laid-Open Patent Application Tokukaihei 03-77430/1991 (published on Apr. 3, 1991) discloses an arrangement for switching the voltage inputted to the input terminal of the offset level control resistor between the upper limit voltage and the lower limit voltage inputted to the input terminal of 2R side. This arrangement realizes a D/A converter with high resolution and high accuracy even without improving accuracy of resistance element.
Here, as the R-2R ladder resistor type D/A converter
70
in
FIG. 8
reveals, in the R-2R ladder resistor type D/A converter, the required number of the unit resister R is calculated as 3n+1 with respect to the bit number n of the digital input signal. Accordingly, the R-2R ladder resistor type D/A converter requires smaller area for resistors compared to a binary resistor type D/A converter (the number of unit resistor is 2
n
−1 with respect to the bit number n), and besides, a D/A converter with high performance can be realized by ensuring only the relative accuracy for the accuracy of the resistor even without ensuring the absolute value. Thus, this mode is advantageous when using as an IC.
However, the relative accuracy between resistors used for the ladder resistor-net in the R-2R ladder resistor type D/A converter is merely about 0.05% without trimming. For this reason, it is difficult to constitute a D/A converter of 10 bits or above only by the R-2R ladder resistor type D/A converter.
In order to increase resolution without costly trimming, two-stage D/A conversion (plural-stages in general) may be performed as with the two-stage D/A converter circuit
90
shown in FIG.
10
. The two-stage D/A converter circuit
90
includes a first stage D/A converter
91
, a second stage R-2R ladder resistor type D/A converter
92
, a latch circuit
93
and a reference voltage generation circuit
94
.
The latch circuit
93
latches digital input data Din in accordance with a clock signal CK, and upper m bit of the latched digital input data Din is inputted to the first stage D/A converter
91
performing first D/A conversion of the two-stage conversion. The first stage D/A converter
91
generates an analog output voltage according to the upper m bit and an analog output voltage according to digital input of the upper m bit+1 from reference voltages VH and VL inputted from the reference voltage generation circuit
94
, and then outputs the voltages respectively as a reference voltages V
L
and a reference voltage V
H
.
Further, lower n bit of the latched digital input data Din is inputted to the second stage R-2R ladder resistor type D/A converter
92
performing second D/A conversion of the two-stage conversion. Further, the second stage R-2R ladder resistor type D/A converter
92
generates a final analog signal Aout of the digital input data Din based on the reference voltages V
L
and V
H
inputted from the first stage D/A converter
91
, and the lower n bit, then outputs the analog signal Aout. The second stage R-2R ladder resistor type D/A converter
92
is made of the R-2R ladder resistor type D/A converter shown in
FIG. 8
, and the reference voltage V
H
, and the reference voltage V
L
are inputted respectively instead of Vdd and GND of FIG.
8
.
The following will explain a resistor string type (also referred to as voltage potentiometer type) D/A converter
91
a
shown in
FIG. 11
as an example of the first stage D/A converter
91
.
FIG. 11
shows an example in which the upper bit of the digital input data Din is 3 bits, i.e., the input and output is carried out in eight-stages. The resistor string type D/A converter
91
a
includes a resistor string
101
, reference voltage switches
102
and
103
, an upper limit reference voltage V
H
buffer amp
104
and a lower limit reference voltage V
L
buffer amp
105
.
The resistor string
101
is a voltage dividing circuit made up of resistors r
0
through r
7
connected in series, and the reference voltage V
H
is inputted to an end of the resistor r
0
side and the reference voltage V
L
is inputted to an end of the resistor r
7
side. The reference voltage switch
102
includes switches SH
0
through SH
7
. These switches are respectively used for sequen
Birch Stewart Kolasch & Birch, LLP.
Sharp Kabushiki Kaisha
Williams Howard L.
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