D/A converter circuit

Details D/A converter circuit D/A converter circuit

2001-10-10

2003-07-08

Young, Brian (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Digital to analog conversion

C341S153000

Reexamination Certificate

active

06590514

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a D/A converter circuit, and more particularly, to a D/A converter circuit provided with resistors that divide the potential difference between a high potential power supply and a low potential power supply to generate divided voltages.
A D/A converter circuit is a circuit for converting a digital signal to an analog signal. The D/A converter circuit may also be used as an internal circuit of an analog-to-digital converter circuit (A/D converter circuit), which converts an analog signal to a digital signal.
FIG. 1
is a schematic circuit diagram of a prior art string-type D/A converter circuit
31
. The D/A converter circuit
31
includes a voltage dividing circuit
32
. The voltage dividing circuit
32
includes a plurality (e.g., six) of resistors R
31
, R
32
, R
33
, R
34
, R
35
, R
36
connected in series between a high potential power supply VD and a lower potential power supply GND. The resistors R
31
-R
36
have the same resistance. Further, the resistors R
31
-R
36
equally divide the potential difference between the high potential power supply VD and the low potential power supply GND to generate divided voltages at nodes N
31
, N
32
, N
33
, N
34
, N
35
between the resistors R
31
-R
36
.
Each of the nodes N
31
-N
35
(nodes connected to the high potential power supply VD and the low potential power supply GND may also be included) is connected to the same output terminal by a switch.
FIG. 1
shows only switches SW
31
, SW
32
respectively connected to nodes N
31
, N
32
. A decoder circuit (not shown) generates an output formed from a digital signal, which has a plurality of bits, to control the activation and inactivation of each switch.
Accordingly, the D/A converter circuit
31
outputs an analog signal OUT
3
having a divided voltage that is applied at the node that is associated with the switch activated by the digital signal of the decoder circuit. A first capacitor C
3
, which is shown in
FIG. 1
, includes the capacitance of each switch and the capacitance of a succeeding stage circuit (not shown), which is connected to the output terminal of the D/A converter circuit
31
.
The D/A converter circuit
31
requires a relatively long period of time from when the activation and inactivation of the switches SW
31
, SW
32
is switched to when the set voltage at node N
36
is generated.
When the digital signal activates the switch SW
31
to output the analog signal OUT
3
at a divided voltage of 5/6×VD, and then the switch SW
31
is inactivated and the switch SW
32
is activated, the divided voltage at node N
32
is lower than that at node N
31
. The discharging of the capacitor C
3
decreases the voltage at node N
36
. This causes the voltage at node N
36
to be substantially the same as that at node N
32
.
On the other hand, when the digital signal activates the switch SW
32
to output the analog signal OUT
3
at a divided voltage of 4/6×VD, and then the switch SW
32
is inactivated and the switch SW
31
is activated, the divided voltage at node N
31
is higher than that at node N
32
. The charging of the capacitor C
3
increases the voltage at node N
36
. This causes the voltage at N
36
to be substantially the same as that at node N
31
.
The converting period of the D/A converter circuit
31
(i.e., the time required for the voltage at node N
36
to stabilize) is determined by the charging/discharging time of the capacitor C
3
. The resistance of the resistors R
31
-R
36
relative to the capacitance C
3
and the ON resistance of each switch determine the charging/discharging time of the capacitor C
3
.
The resistance of the resistors R
31
-R
36
and the ON resistance of the switches SW
31
, SW
32
may be decreased to reduce the discharging or charging time of the capacitor C
3
and shorten the converting time. However, a decrease in the resistance of the resistors R
31
-R
36
increases the current consumption between the high potential power supply VD and the low potential power supply GND. Further, a decrease in the ON resistance of each switch increases the size of the switch, which increases the capacitance component of the switch. As a result, the capacitance of the capacitor C
3
increases and hinders reduction of the converting time.
SUMMARY OF THE INVENTION
The object of the present invention is to provide a D/A converter circuit that reduces the time for converting a digital signal to an analog signal.
To achieve the above object, the present invention provides a D/A converter circuit including a plurality of impedance elements connected in series between a first power supply and a second power supply and a plurality of switch groups including a first switch group and a second switch group. The first switch group is formed by a plurality of first switches connected to at least a plurality of nodes between the plurality of impedance elements, and the second switch group is formed by a plurality of second switches connected to at least the plurality of nodes. A control circuit is connected to the switch groups for selectively closing one of the first switches and one of the second switches.
A further perspective of the present invention is a D/A converter circuit including a plurality of resistors connected in series between a first power supply and a second power supply. The plurality of resistors include a first resistor adjacent to the first power supply and a second resistor adjacent to the second power supply. A first switch group is formed by a plurality of first switches connected to a plurality of inter-resistor nodes between the resistors and to a first inter-power source node between the first power supply and the first resistor. A second switch group is formed by a plurality of second switches connected to the inter-resistor nodes and to a second inter-power source node between the second power source and the second resistor. A decoder circuit is connected to the first and second switch groups to selectively close one of the first switches and one of the second switches.
Other aspects and advantages of the present invention will become apparent from the following description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.


REFERENCES:
patent: 6049300 (2000-04-01), Shoval
patent: 6163289 (2000-12-01), Ginetti
patent: 6340939 (2002-01-01), Dedic

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