D/A converter and delta-sigma D/A converter

Details D/A converter and delta-sigma D/A converter D/A converter and delta-sigma D/A converter

2003-03-24

2004-02-17

Tokar, Michael (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Digital to analog conversion

C341S143000, C341S144000

Reexamination Certificate

active

06693574

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to D/A converters which convert digital signals into analog signals and are used for signal processing in the field of audio equipment and the like. In particular, it relates to a switched capacitor D/A converter capable of operating at a low supply voltage and outputting analog signals low inharmonic components and noise components, and to a delta-sigma D/A converter using thereof.
2. Description of the Prior Art
In an audio area, a so-called delta-sigma D/A converter, for example, such as the one shown in
FIG. 6
has been proposed as a signal converter which converts high-bit (16-bit) digital input signals used, for example, in compact disks (CDs) into analog output signals. The signal converter
10
interpolates high-bit (16-bit) digital input signals 64 to 128 times using a digital filter
11
. Then, a digital delta-sigma modulator
12
converts the interpolated digital signals into lower-bit (lower-resolution) digital signals. Then, a signal control circuit
13
converts the digital signals into digital data suitable for controlling a switched capacitor D/A converter
15
in the next stage, and the switched capacitor D/A converter
15
produces analog output signals.
Regarding the switched capacitor D/A converter
15
, various types have been proposed. For example, a switched capacitor D/A converter
40
described in Japanese Patent Laid-Open No. 11-055121 applied by this applicant comprises an operational amplifier
100
whose output terminal and inverting input terminal are connected by a capacitive element Cfb and whose non-inverting input terminal is connected to an analog ground, as shown in FIG.
7
. Also, it comprises capacitive elements C
1
to Ci; a switch SB connected between the capacitive elements C
1
to Ci and the inverting input terminal of the operational amplifier
100
; switches SU
1
to SUi which connect the right terminals of the respective capacitive elements C
1
to Ci, i.e., the terminals connected with the switch SB, to the analog ground; switches SUG
1
to SUGi which connect the left terminals of the capacitive elements C
1
to Ci with one of reference voltages (Vr+ and Vr−); switches SY
1
to SYi connected between the left terminals of the respective capacitive elements C
1
to Ci and the output terminal of the operational amplifier
100
; and a clock supplier
200
which supplies two types of clock &phgr;
1
and &phgr;
2
.
The capacitive elements C
1
to Ci hold charges which correspond to a predetermined reference voltage based on digital data during a first period and the capacitive elements C
1
to Ci are connected between the inverting input terminal and output terminal of the operational amplifier
100
during a second period.
Specifically, when the clock &phgr;
1
is in high state, the capacitive element Cx is operated according to the polarity of digital data Sx (x=1 to i). For example, if the digital data Sx is “1,” the capacitive element Cx is connected between the reference voltage Vr+ and analog ground and positive charges are sampled onto the capacitive element Cx. If the digital data Sx is “−1,” the capacitive element Cx is connected between the reference voltage Vr− and digital ground and negative charges are sampled. When the clock &phgr;
2
is in high state, the capacitive element Cx is connected between the output terminal and inverting input terminal of the operational amplifier
100
.
When the switched capacitor D/A converter
40
shown in
FIG. 7
is implemented as a MOS integrated circuit and operated at a positive power supply potential VDD and a negative power supply potential 0 [V], a high reference voltage is used and so-called kT/C noise attributable to sampling by capacitive elements is reduced to maximize S/N ratio. Besides, to simplify configuration, the reference voltage Vr+ is set at VDD, the reference voltage Vr− is set at 0 [V], and the analog ground is set at the midpoint potential (½)·VDD of the supply voltage.
FIG. 8
shows potentials of various parts around the capacitive element Ci. In
FIG. 8A
, where the reference voltage Vr+ is selected, the switch SUGi which connects the capacitive element Ci with one of the reference voltages (Vr+ and Vr−) corresponds to a MOS switch Q
1
consisting of a MOS transistor while the switch SUi which connects the capacitive element Ci to the analog ground corresponds to a MOS switch Q
2
. In
FIG. 8B
, where the reference voltage Vr− is selected, the switch SUi corresponds to a MOS switch Q
3
while the switch SUGi corresponds to a MOS switch Q
4
.
If the MOS switches Q
2
and Q
3
connected to the analog ground consist of n-channel MOS transistors as shown in
FIGS. 8A and 8B
, the source potential is (½)·VDD. If the gate potential is VDD, the gate-source potential VGS of the MOS switches Q
2
and Q
3
is (½)·VDD.
However, if the MOS integrated circuit is operated at a low supply voltage, since the switches (Q
2
and Q
3
, in this case) connected to the analog ground consist of MOS transistors, the MOS switches may not turn on and charges may not be able to be sampled onto the capacitive elements during the first period depending on relationship between the gate-source voltage VGS and a threshold voltage VT of the MOS transistors.
FIG. 9
shows correspondence between source potential and resistance (so-called ON resistance) when n-channel MOS transistors of the same size conduct at different supply voltages. In
FIG. 9
, the horizontal axis represents the source potential while the vertical axis represents the ON resistance. A characteristic line L
1
has the lowest supply voltage VDD and the rightmost characteristic line has the highest supply voltage VDD. The ON resistances of the characteristic lines L
1
to L
3
at the source voltage of (½)·VDD are indicated by ◯ marks.
As shown in
FIG. 9
, the ON resistance at the source voltage of (½)·VDD rises sharply as the supply voltage VDD lowers. Thus, in order to sample charges within a predetermined period of time, the size of the MOS transistors must be increased to lower the ON resistance.
However, increasing the size of the MOS transistors which compose switches will increase the feed-through noise produced when the gate voltage changes during sampling of charges and the switches are turned off. This will cause variations in the amount of charge among samplings, making the operational amplifier
100
produce harmonics and/or noise.
Even if changes in the threshold voltage VT due to a substrate effect are ignored, if the gate-source voltage, i.e., (½)·VDD, is not higher than the threshold voltage VT, MOS switches do not turn on, and thus the minimum operating supply voltage VDD is VDD=2·VT.
Similarly, if the switches connected to the analog ground consist of p-channel MOS transistors, since the MOS switches Q
2
and Q
3
in
FIG. 8A
are p-channel MOS transistors, the gate-source voltage VGS is (½)·VDD as with the above case. Thus, if (½)·VDD is not higher than the threshold voltage VT, the MOS switches Q
2
and Q
3
do not turn on, and thus the minimum operating supply voltage VDD is VDD=2·VT. Incidentally, the threshold voltage VT of p-channel MOS transistors is negative, and its absolute value is used here.
If the MOS switches Q
2
and Q
3
connected to the analog ground consist of an n-channel MOS transistor and p-channel MOS transistor connected in parallel, the gate-source voltage VGS of the MOS transistors is also (½)·VDD. Thus, if the gate-source voltage VGS lowers below the lower of the threshold voltages VT of the two MOS transistors which compose the MOS switches, MOS switches do not turn on, so the minimum operating supply voltage VDD is determined based on the lower of the threshold voltages VT. In short, the minimum operating supply voltage VDD is restricted by the threshold voltages VT of the MOS switches.
Thus, the object of the present invention is to pro

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