D/A conversion method and D/A converter

Details D/A conversion method and D/A converter D/A conversion method and D/A converter

2000-09-28

2002-10-15

Jeanpierre, Pegut (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Digital to analog conversion

C341S136000, C341S138000

Reexamination Certificate

active

06466148

ABSTRACT:

BACKGROUND
The present invention relates to a digital-to-analog (D/A) conversion method and a D/A converter.
Typical conventional D/A converters are described in D. A. Johns and K. Martin, “Integrated Analog Circuit Design”, John Wiley & Sons, New York 1997, pp. 469-484. A common type uses exponential weights (typically current, voltage or charge sources representing the weights 2
k
of a digital number in conventional binary representation). In order to improve matching of the weights, these weights are often implemented as an array of unit weights. As discussed in Integrated Analog Circuit Design, a drawback of exponentially weighted D/A converters is the glitches that occur at so called major code transitions, such as between 011 . . . 1 and 100 . . . 0. Due to slight switching delays the output signal may, during a short time period, correspond to either the value 111 . . . 1 (maximum value) or 000 . . . 0 (minimum value). This effect is referred to as a glitch and becomes particularly disturbing at high-speed operation of the converter.
Integrated Analog Circuit Design also discusses suggested solutions to reduce glitching noise. One such solution is based on thermometer code or unary weighted code. This solution significantly reduces glitching noise, but requires complex decoders and extra logic at the unit weights.
Integrated Analog Circuit Design also discusses hybrids between these approaches. These hybrids are referred to as segmented D/A converters. Such converters typically use unary weights for a few of the most significant bits (MSB) and exponential weights for the remaining least significant bits (LSB). This solution also requires complex decoders and extra logic at the unit weights.
A variation of the hybrid converters discussed above is described in U.S. Pat. No.4,910,514. In this implementation unary weighting is used by both the most and least significant bits, but with different weights. This implementation has the same drawbacks as the hybrid implementation.
SUMMARY
An object of the present invention is to provide a D/A conversion method and a D/A converter that reduce glitching noise and yet are less complex than the prior art
This object is achieved in accordance with the attached claims.
Briefly, the present invention is based on linearly weighting instead of exponential or unary weighting. At high bit-resolution this gives excellent glitching performance at low complexity. Furthermore, this principle also easily provides redundancy, thereby significantly reducing systematic errors due to unit weight-mismatch.


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D. A. Johns and K. Martin, “Integrated analog circuit design”, John Wiley & Sons, New York, 1997, pp. 469-484.

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